92b5a3405d
This change continues with the line of work discussed in https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structure-policy-variants/71295. In D153155, we started removing the legacy distinction between unsuffixed (TA) and _TU pseudos. This patch continues that effort for the unary instruction families. The change consists of a few interacting pieces: * Adding a vector policy operand to VPseudoUnaryNoMaskTU. * Then using VPseudoUnaryNoMaskTU for all cases where VPseudoUnaryNoMask was previously used and deleting the unsuffixed form. * Then renaming VPseudoUnaryNoMaskTU to VPseudoUnaryNoMask, and adjusting the RISCVMaskedPseudo table to use the combined pseudo. * Fixing up two places in C++ code which manually construct VMV_V_* instructions. Normally, I'd try to factor this into a couple of changes, but in this case, the table structure is tied to naming and thus we can't really separate the otherwise NFC bits. As before, we see codegen changes (some improvements and some regressions) due to scheduling differences caused by the extra implicit_def instructions. Differential Revision: https://reviews.llvm.org/D153899
227 lines
11 KiB
YAML
227 lines
11 KiB
YAML
# RUN: llc -mtriple riscv64 -mattr=+m,+v -run-pass=prologepilog \
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# RUN: -riscv-v-vector-bits-min=512 -o - %s | FileCheck %s
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#
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# Stack layout of this program
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# |--------------------------| -- <-- Incoming SP
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# | a7 (Vaarg) |
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# | ------------------------ | -- <-- New SP + vlenb + 72
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# | a6 (Vaarg) |
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# | ------------------------ | -- <-- New SP + vlenb + 64
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# | ra (Callee-saved reg) |
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# | ------------------------ | -- <-- New SP + vlenb + 56
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# | s0 (Callee-saved reg) |
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# | ------------------------ | -- <-- New SP + vlenb + 48
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# | s1 (Callee-saved reg) |
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# | ------------------------ | -- <-- New SP + vlenb + 40
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# | 8 bytes of padding |
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# | ------------------------ | -- <-- New SP + vlenb
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# | v8 (RVV objects) |
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# | ------------------------ | -- <-- New SP + 32
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# | buf1 |
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# |--------------------------| -- <-- New SP + 16
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# | Stack ID 5 |
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# |--------------------------| -- <-- New SP + 8
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# | Stack ID 6 |
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# |--------------------------| -- <-- New SP
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--- |
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; ModuleID = 'wrong-stack-offset-for-rvv-object.ll'
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source_filename = "wrong-stack-offset-for-rvv-object.ll"
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "riscv64"
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%struct = type { i32 }
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define void @asm_fprintf(%struct %file, i8* %p, [10 x i8]* %buf, i8* %arrayidx3, <2 x i8>* %0, i8* %1, ...) #0 {
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entry:
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%buf1 = alloca [10 x i8], i32 0, align 8
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%arrayidx32 = getelementptr inbounds [10 x i8], [10 x i8]* %buf, i64 0, i64 1
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br label %while.cond
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while.cond: ; preds = %while.cond, %sw.bb, %entry
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%incdec.ptr = getelementptr inbounds i8, i8* undef, i64 1
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%2 = load i8, i8* null, align 1
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%3 = zext i8 0 to i64
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%cond = icmp eq i64 %3, 0
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br i1 %cond, label %sw.bb, label %while.cond
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sw.bb: ; preds = %while.cond
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%4 = load i8, i8* null, align 1
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store <2 x i8> zeroinitializer, <2 x i8>* %0, align 1
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%call = call i32 (i8*, ...) @fprintf(i8* %p)
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br label %while.cond
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}
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declare i32 @fprintf(i8*, ...) #0
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attributes #0 = { "target-features"="+m,+v" }
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...
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---
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name: asm_fprintf
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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failsVerification: false
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tracksDebugUserValues: true
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registers: []
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liveins:
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- { reg: '$x11', virtual-reg: '' }
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- { reg: '$x14', virtual-reg: '' }
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- { reg: '$x16', virtual-reg: '' }
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- { reg: '$x17', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 8
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adjustsStack: false
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hasCalls: true
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stackProtector: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack:
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- { id: 0, type: default, offset: -8, size: 8, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, type: default, offset: -16, size: 8, alignment: 16, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, type: default, offset: -16, size: 8, alignment: 16, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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stack:
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- { id: 0, name: buf1, type: default, offset: 0, size: 1, alignment: 8,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
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stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo:
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varArgsFrameIndex: -1
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varArgsSaveSize: 16
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body: |
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; CHECK-LABEL: name: asm_fprintf
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; CHECK: stack:
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; CHECK-NEXT: - { id: 0, name: buf1, type: default, offset: -48, size: 1, alignment: 8,
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; CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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; CHECK-NEXT: - { id: 1, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
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; CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
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; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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; CHECK-NEXT: - { id: 2, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8,
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; CHECK-NEXT: stack-id: default, callee-saved-register: '$x1', callee-saved-restored: true,
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; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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; CHECK-NEXT: - { id: 3, name: '', type: spill-slot, offset: -32, size: 8, alignment: 8,
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; CHECK-NEXT: stack-id: default, callee-saved-register: '$x8', callee-saved-restored: true,
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; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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; CHECK-NEXT: - { id: 4, name: '', type: spill-slot, offset: -40, size: 8, alignment: 8,
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; CHECK-NEXT: stack-id: default, callee-saved-register: '$x9', callee-saved-restored: true,
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; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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; CHECK-NEXT: - { id: 5, name: '', type: default, offset: -56, size: 8, alignment: 8,
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; CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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; CHECK-NEXT: - { id: 6, name: '', type: default, offset: -64, size: 8, alignment: 8,
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; CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $x11, $x14, $x16, $x17, $x1, $x8, $x9
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -80
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 80
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; CHECK-NEXT: SD killed $x1, $x2, 56 :: (store (s64) into %stack.2)
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; CHECK-NEXT: SD killed $x8, $x2, 48 :: (store (s64) into %stack.3)
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; CHECK-NEXT: SD killed $x9, $x2, 40 :: (store (s64) into %stack.4)
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -24
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -32
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -40
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; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB
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; CHECK-NEXT: $x10 = frame-setup SLLI killed $x10, 1
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; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22
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; CHECK-NEXT: renamable $x8 = COPY $x14
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; CHECK-NEXT: renamable $x9 = COPY $x11
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; CHECK-NEXT: $x10 = PseudoReadVLENB
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; CHECK-NEXT: $x10 = SLLI killed $x10, 1
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; CHECK-NEXT: $x10 = ADD $x2, killed $x10
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; CHECK-NEXT: SD killed renamable $x17, killed $x10, 72 :: (store (s64))
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; CHECK-NEXT: $x10 = PseudoReadVLENB
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; CHECK-NEXT: $x10 = SLLI killed $x10, 1
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; CHECK-NEXT: $x10 = ADD $x2, killed $x10
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; CHECK-NEXT: SD killed renamable $x16, killed $x10, 64 :: (store (s64) into %fixed-stack.1, align 16)
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; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_MF8 undef $v8, 0, 2, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: $x10 = ADDI $x2, 32
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; CHECK-NEXT: VS1R_V killed renamable $v8, killed $x10 :: (store unknown-size into %stack.1, align 8)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.while.cond:
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; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000)
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; CHECK-NEXT: liveins: $x8, $x9
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: BNE $x0, $x0, %bb.1
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; CHECK-NEXT: PseudoBR %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.sw.bb:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $x8, $x9
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: $x10 = ADDI $x2, 32
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; CHECK-NEXT: renamable $v8 = VL1RE8_V killed $x10 :: (load unknown-size from %stack.1, align 8)
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; CHECK-NEXT: PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3 /* e8 */, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1)
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; CHECK-NEXT: $x10 = COPY renamable $x9
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; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10
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; CHECK-NEXT: PseudoBR %bb.1
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $x11, $x14, $x16, $x17
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renamable $x8 = COPY $x14
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renamable $x9 = COPY $x11
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SD killed renamable $x17, %fixed-stack.0, 0 :: (store (s64))
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SD killed renamable $x16, %fixed-stack.1, 0 :: (store (s64) into %fixed-stack.1, align 16)
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dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype
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renamable $v8 = PseudoVMV_V_I_MF8 undef $v8, 0, 2, 3, 0, implicit $vl, implicit $vtype
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VS1R_V killed renamable $v8, %stack.1 :: (store unknown-size into %stack.1, align 8)
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bb.1.while.cond:
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successors: %bb.2(0x30000000), %bb.1(0x50000000)
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liveins: $x8, $x9
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BNE $x0, $x0, %bb.1
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PseudoBR %bb.2
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bb.2.sw.bb:
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successors: %bb.1(0x80000000)
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liveins: $x8, $x9
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dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype
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renamable $v8 = VL1RE8_V %stack.1 :: (load unknown-size from %stack.1, align 8)
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PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1)
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ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
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$x10 = COPY renamable $x9
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PseudoCALL target-flags(riscv-plt) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10
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ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
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PseudoBR %bb.1
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...
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