e4a4122eb6
Remove support for zext and sext constant expressions. All places creating them have been removed beforehand, so this just removes the APIs and uses of these constant expressions in tests. There is some additional cleanup that can be done on top of this, e.g. we can remove the ZExtInst vs ZExtOperator footgun. This is part of https://discourse.llvm.org/t/rfc-remove-most-constant-expressions/63179.
606 lines
24 KiB
LLVM
606 lines
24 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-win64 | FileCheck %s
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; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS
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; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S -stress-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS
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; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE
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; rdar://7304838
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; CodeGenPrepare should move the zext into the block with the load
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; so that SelectionDAG can select it with the load.
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;
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; CHECK-LABEL: foo:
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; CHECK: movsbl ({{%rdi|%rcx}}), %eax
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define void @foo(ptr %p, ptr %q) {
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; OPTALL-LABEL: define void @foo(
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; OPTALL-SAME: ptr [[P:%.*]], ptr [[Q:%.*]]) {
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; OPTALL-NEXT: entry:
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; OPTALL-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; OPTALL-NEXT: [[S:%.*]] = zext i8 [[T]] to i32
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; OPTALL-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; OPTALL-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; OPTALL: true:
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; OPTALL-NEXT: store i32 [[S]], ptr [[Q]], align 4
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; OPTALL-NEXT: ret void
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; OPTALL: false:
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; OPTALL-NEXT: ret void
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;
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entry:
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%t = load i8, ptr %p
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i8 %t to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a zextload is an operation with only one
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; argument to explicitly extend is in the way.
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; Make sure the operation is not promoted when the promotion pass is disabled.
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define void @promoteOneArg(ptr %p, ptr %q) {
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; OPT-LABEL: define void @promoteOneArg(
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; OPT-SAME: ptr [[P:%.*]], ptr [[Q:%.*]]) {
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; OPT-NEXT: entry:
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; OPT-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; OPT-NEXT: [[S:%.*]] = zext i8 [[T]] to i32
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; OPT-NEXT: [[ADD:%.*]] = add nuw i32 [[S]], 2
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; OPT-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; OPT-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; OPT: true:
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; OPT-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
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; OPT-NEXT: ret void
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; OPT: false:
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; OPT-NEXT: ret void
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;
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; DISABLE-LABEL: define void @promoteOneArg(
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; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]]) {
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; DISABLE-NEXT: entry:
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; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; DISABLE-NEXT: [[ADD:%.*]] = add nuw i8 [[T]], 2
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; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; DISABLE: true:
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; DISABLE-NEXT: [[S:%.*]] = zext i8 [[ADD]] to i32
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; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
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; DISABLE-NEXT: ret void
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; DISABLE: false:
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; DISABLE-NEXT: ret void
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;
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entry:
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%t = load i8, ptr %p
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%add = add nuw i8 %t, 2
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i8 %add to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a sextload is an operation with only one
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; argument to explicitly extend is in the way.
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; Version with sext.
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define void @promoteOneArgSExt(ptr %p, ptr %q) {
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; OPT-LABEL: define void @promoteOneArgSExt(
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; OPT-SAME: ptr [[P:%.*]], ptr [[Q:%.*]]) {
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; OPT-NEXT: entry:
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; OPT-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; OPT-NEXT: [[S:%.*]] = sext i8 [[T]] to i32
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; OPT-NEXT: [[ADD:%.*]] = add nsw i32 [[S]], 2
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; OPT-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; OPT-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; OPT: true:
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; OPT-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
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; OPT-NEXT: ret void
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; OPT: false:
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; OPT-NEXT: ret void
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;
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; DISABLE-LABEL: define void @promoteOneArgSExt(
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; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]]) {
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; DISABLE-NEXT: entry:
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; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; DISABLE-NEXT: [[ADD:%.*]] = add nsw i8 [[T]], 2
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; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; DISABLE: true:
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; DISABLE-NEXT: [[S:%.*]] = sext i8 [[ADD]] to i32
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; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
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; DISABLE-NEXT: ret void
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; DISABLE: false:
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; DISABLE-NEXT: ret void
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;
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entry:
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%t = load i8, ptr %p
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%add = add nsw i8 %t, 2
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = sext i8 %add to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a zextload is an operation with two
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; arguments to explicitly extend is in the way.
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; Extending %add will create two extensions:
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; 1. One for %b.
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; 2. One for %t.
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; #1 will not be removed as we do not know anything about %b.
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; #2 may not be merged with the load because %t is used in a comparison.
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; Since two extensions may be emitted in the end instead of one before the
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; transformation, the regular heuristic does not apply the optimization.
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define void @promoteTwoArgZext(ptr %p, ptr %q, i8 %b) {
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; NONSTRESS-LABEL: define void @promoteTwoArgZext(
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; NONSTRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]]) {
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; NONSTRESS-NEXT: entry:
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; NONSTRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; NONSTRESS-NEXT: [[ADD:%.*]] = add nuw i8 [[T]], [[B]]
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; NONSTRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; NONSTRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; NONSTRESS: true:
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; NONSTRESS-NEXT: [[S:%.*]] = zext i8 [[ADD]] to i32
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; NONSTRESS-NEXT: store i32 [[S]], ptr [[Q]], align 4
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; NONSTRESS-NEXT: ret void
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; NONSTRESS: false:
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; NONSTRESS-NEXT: ret void
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;
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; STRESS-LABEL: define void @promoteTwoArgZext(
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; STRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]]) {
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; STRESS-NEXT: entry:
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; STRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; STRESS-NEXT: [[S:%.*]] = zext i8 [[T]] to i32
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; STRESS-NEXT: [[PROMOTED:%.*]] = zext i8 [[B]] to i32
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; STRESS-NEXT: [[ADD:%.*]] = add nuw i32 [[S]], [[PROMOTED]]
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; STRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; STRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; STRESS: true:
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; STRESS-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
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; STRESS-NEXT: ret void
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; STRESS: false:
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; STRESS-NEXT: ret void
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;
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; DISABLE-LABEL: define void @promoteTwoArgZext(
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; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]]) {
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; DISABLE-NEXT: entry:
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; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; DISABLE-NEXT: [[ADD:%.*]] = add nuw i8 [[T]], [[B]]
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; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; DISABLE: true:
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; DISABLE-NEXT: [[S:%.*]] = zext i8 [[ADD]] to i32
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; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
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; DISABLE-NEXT: ret void
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; DISABLE: false:
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; DISABLE-NEXT: ret void
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;
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entry:
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%t = load i8, ptr %p
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%add = add nuw i8 %t, %b
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i8 %add to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a sextload is an operation with two
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; arguments to explicitly extend is in the way.
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; Version with sext.
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define void @promoteTwoArgSExt(ptr %p, ptr %q, i8 %b) {
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; NONSTRESS-LABEL: define void @promoteTwoArgSExt(
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; NONSTRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]]) {
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; NONSTRESS-NEXT: entry:
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; NONSTRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; NONSTRESS-NEXT: [[ADD:%.*]] = add nsw i8 [[T]], [[B]]
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; NONSTRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; NONSTRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; NONSTRESS: true:
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; NONSTRESS-NEXT: [[S:%.*]] = sext i8 [[ADD]] to i32
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; NONSTRESS-NEXT: store i32 [[S]], ptr [[Q]], align 4
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; NONSTRESS-NEXT: ret void
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; NONSTRESS: false:
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; NONSTRESS-NEXT: ret void
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;
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; STRESS-LABEL: define void @promoteTwoArgSExt(
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; STRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]]) {
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; STRESS-NEXT: entry:
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; STRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; STRESS-NEXT: [[S:%.*]] = sext i8 [[T]] to i32
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; STRESS-NEXT: [[PROMOTED:%.*]] = sext i8 [[B]] to i32
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; STRESS-NEXT: [[ADD:%.*]] = add nsw i32 [[S]], [[PROMOTED]]
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; STRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; STRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; STRESS: true:
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; STRESS-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
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; STRESS-NEXT: ret void
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; STRESS: false:
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; STRESS-NEXT: ret void
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;
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; DISABLE-LABEL: define void @promoteTwoArgSExt(
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; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]]) {
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; DISABLE-NEXT: entry:
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; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; DISABLE-NEXT: [[ADD:%.*]] = add nsw i8 [[T]], [[B]]
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; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; DISABLE: true:
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; DISABLE-NEXT: [[S:%.*]] = sext i8 [[ADD]] to i32
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; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
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; DISABLE-NEXT: ret void
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; DISABLE: false:
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; DISABLE-NEXT: ret void
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;
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entry:
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%t = load i8, ptr %p
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%add = add nsw i8 %t, %b
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = sext i8 %add to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we do not a zextload if we need to introduce more than
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; one additional extension.
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define void @promoteThreeArgZext(ptr %p, ptr %q, i8 %b, i8 %c) {
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; NONSTRESS-LABEL: define void @promoteThreeArgZext(
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; NONSTRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]], i8 [[C:%.*]]) {
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; NONSTRESS-NEXT: entry:
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; NONSTRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; NONSTRESS-NEXT: [[TMP:%.*]] = add nuw i8 [[T]], [[B]]
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; NONSTRESS-NEXT: [[ADD:%.*]] = add nuw i8 [[TMP]], [[C]]
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; NONSTRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; NONSTRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; NONSTRESS: true:
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; NONSTRESS-NEXT: [[S:%.*]] = zext i8 [[ADD]] to i32
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; NONSTRESS-NEXT: store i32 [[S]], ptr [[Q]], align 4
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; NONSTRESS-NEXT: ret void
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; NONSTRESS: false:
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; NONSTRESS-NEXT: ret void
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;
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; STRESS-LABEL: define void @promoteThreeArgZext(
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; STRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]], i8 [[C:%.*]]) {
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; STRESS-NEXT: entry:
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; STRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; STRESS-NEXT: [[S:%.*]] = zext i8 [[T]] to i32
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; STRESS-NEXT: [[PROMOTED1:%.*]] = zext i8 [[B]] to i32
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; STRESS-NEXT: [[TMP:%.*]] = add nuw i32 [[S]], [[PROMOTED1]]
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; STRESS-NEXT: [[PROMOTED:%.*]] = zext i8 [[C]] to i32
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; STRESS-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP]], [[PROMOTED]]
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; STRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; STRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; STRESS: true:
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; STRESS-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
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; STRESS-NEXT: ret void
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; STRESS: false:
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; STRESS-NEXT: ret void
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;
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; DISABLE-LABEL: define void @promoteThreeArgZext(
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; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]], i8 [[C:%.*]]) {
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; DISABLE-NEXT: entry:
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; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; DISABLE-NEXT: [[TMP:%.*]] = add nuw i8 [[T]], [[B]]
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; DISABLE-NEXT: [[ADD:%.*]] = add nuw i8 [[TMP]], [[C]]
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; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; DISABLE: true:
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; DISABLE-NEXT: [[S:%.*]] = zext i8 [[ADD]] to i32
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; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
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; DISABLE-NEXT: ret void
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; DISABLE: false:
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; DISABLE-NEXT: ret void
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;
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entry:
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%t = load i8, ptr %p
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%tmp = add nuw i8 %t, %b
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%add = add nuw i8 %tmp, %c
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i8 %add to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a zextload after promoting and merging
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; two extensions.
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define void @promoteMergeExtArgZExt(ptr %p, ptr %q, i16 %b) {
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; NONSTRESS-LABEL: define void @promoteMergeExtArgZExt(
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; NONSTRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i16 [[B:%.*]]) {
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; NONSTRESS-NEXT: entry:
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; NONSTRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; NONSTRESS-NEXT: [[EXT:%.*]] = zext i8 [[T]] to i16
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; NONSTRESS-NEXT: [[ADD:%.*]] = add nuw i16 [[EXT]], [[B]]
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; NONSTRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; NONSTRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; NONSTRESS: true:
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; NONSTRESS-NEXT: [[S:%.*]] = zext i16 [[ADD]] to i32
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; NONSTRESS-NEXT: store i32 [[S]], ptr [[Q]], align 4
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; NONSTRESS-NEXT: ret void
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; NONSTRESS: false:
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; NONSTRESS-NEXT: ret void
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;
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; STRESS-LABEL: define void @promoteMergeExtArgZExt(
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; STRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i16 [[B:%.*]]) {
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; STRESS-NEXT: entry:
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; STRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; STRESS-NEXT: [[PROMOTED1:%.*]] = zext i8 [[T]] to i32
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; STRESS-NEXT: [[PROMOTED:%.*]] = zext i16 [[B]] to i32
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; STRESS-NEXT: [[ADD:%.*]] = add nuw i32 [[PROMOTED1]], [[PROMOTED]]
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; STRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; STRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; STRESS: true:
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; STRESS-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
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; STRESS-NEXT: ret void
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; STRESS: false:
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; STRESS-NEXT: ret void
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;
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; DISABLE-LABEL: define void @promoteMergeExtArgZExt(
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; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i16 [[B:%.*]]) {
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; DISABLE-NEXT: entry:
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; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
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; DISABLE-NEXT: [[EXT:%.*]] = zext i8 [[T]] to i16
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; DISABLE-NEXT: [[ADD:%.*]] = add nuw i16 [[EXT]], [[B]]
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; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
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; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
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; DISABLE: true:
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; DISABLE-NEXT: [[S:%.*]] = zext i16 [[ADD]] to i32
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; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
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; DISABLE-NEXT: ret void
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; DISABLE: false:
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; DISABLE-NEXT: ret void
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;
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entry:
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%t = load i8, ptr %p
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%ext = zext i8 %t to i16
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|
%add = add nuw i16 %ext, %b
|
|
%a = icmp slt i8 %t, 20
|
|
br i1 %a, label %true, label %false
|
|
true:
|
|
%s = zext i16 %add to i32
|
|
store i32 %s, ptr %q
|
|
ret void
|
|
false:
|
|
ret void
|
|
}
|
|
|
|
; Check that we manage to form a sextload after promoting and merging
|
|
; two extensions.
|
|
; Version with sext.
|
|
define void @promoteMergeExtArgSExt(ptr %p, ptr %q, i16 %b) {
|
|
; NONSTRESS-LABEL: define void @promoteMergeExtArgSExt(
|
|
; NONSTRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i16 [[B:%.*]]) {
|
|
; NONSTRESS-NEXT: entry:
|
|
; NONSTRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
|
|
; NONSTRESS-NEXT: [[EXT:%.*]] = zext i8 [[T]] to i16
|
|
; NONSTRESS-NEXT: [[ADD:%.*]] = add nsw i16 [[EXT]], [[B]]
|
|
; NONSTRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
|
|
; NONSTRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
|
|
; NONSTRESS: true:
|
|
; NONSTRESS-NEXT: [[S:%.*]] = sext i16 [[ADD]] to i32
|
|
; NONSTRESS-NEXT: store i32 [[S]], ptr [[Q]], align 4
|
|
; NONSTRESS-NEXT: ret void
|
|
; NONSTRESS: false:
|
|
; NONSTRESS-NEXT: ret void
|
|
;
|
|
; STRESS-LABEL: define void @promoteMergeExtArgSExt(
|
|
; STRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i16 [[B:%.*]]) {
|
|
; STRESS-NEXT: entry:
|
|
; STRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
|
|
; STRESS-NEXT: [[PROMOTED1:%.*]] = zext i8 [[T]] to i32
|
|
; STRESS-NEXT: [[PROMOTED:%.*]] = sext i16 [[B]] to i32
|
|
; STRESS-NEXT: [[ADD:%.*]] = add nsw i32 [[PROMOTED1]], [[PROMOTED]]
|
|
; STRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
|
|
; STRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
|
|
; STRESS: true:
|
|
; STRESS-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
|
|
; STRESS-NEXT: ret void
|
|
; STRESS: false:
|
|
; STRESS-NEXT: ret void
|
|
;
|
|
; DISABLE-LABEL: define void @promoteMergeExtArgSExt(
|
|
; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i16 [[B:%.*]]) {
|
|
; DISABLE-NEXT: entry:
|
|
; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
|
|
; DISABLE-NEXT: [[EXT:%.*]] = zext i8 [[T]] to i16
|
|
; DISABLE-NEXT: [[ADD:%.*]] = add nsw i16 [[EXT]], [[B]]
|
|
; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
|
|
; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
|
|
; DISABLE: true:
|
|
; DISABLE-NEXT: [[S:%.*]] = sext i16 [[ADD]] to i32
|
|
; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
|
|
; DISABLE-NEXT: ret void
|
|
; DISABLE: false:
|
|
; DISABLE-NEXT: ret void
|
|
;
|
|
entry:
|
|
%t = load i8, ptr %p
|
|
%ext = zext i8 %t to i16
|
|
%add = add nsw i16 %ext, %b
|
|
%a = icmp slt i8 %t, 20
|
|
br i1 %a, label %true, label %false
|
|
true:
|
|
%s = sext i16 %add to i32
|
|
store i32 %s, ptr %q
|
|
ret void
|
|
false:
|
|
ret void
|
|
}
|
|
|
|
; Check that we manage to catch all the extload opportunities that are exposed
|
|
; by the different iterations of codegen prepare.
|
|
; Moreover, check that we do not promote more than we need to.
|
|
; Here is what is happening in this test (not necessarly in this order):
|
|
; 1. We try to promote the operand of %sextadd.
|
|
; a. This creates one sext of %ld2 and one of %zextld
|
|
; b. The sext of %ld2 can be combine with %ld2, so we remove one sext but
|
|
; introduced one. This is fine with the current heuristic: neutral.
|
|
; => We have one zext of %zextld left and we created one sext of %ld2.
|
|
; 2. We try to promote the operand of %sextaddza.
|
|
; a. This creates one sext of %zexta and one of %zextld
|
|
; b. The sext of %zexta can be combined with the zext of %a.
|
|
; c. The sext of %zextld leads to %ld and can be combined with it. This is
|
|
; done by promoting %zextld. This is fine with the current heuristic:
|
|
; neutral.
|
|
; => We have created a new zext of %ld and we created one sext of %zexta.
|
|
; 3. We try to promote the operand of %sextaddb.
|
|
; a. This creates one sext of %b and one of %zextld
|
|
; b. The sext of %b is a dead-end, nothing to be done.
|
|
; c. Same thing as 2.c. happens.
|
|
; => We have created a new zext of %ld and we created one sext of %b.
|
|
; 4. We try to promote the operand of the zext of %zextld introduced in #1.
|
|
; a. Same thing as 2.c. happens.
|
|
; b. %zextld does not have any other uses. It is dead coded.
|
|
; => We have created a new zext of %ld and we removed a zext of %zextld and
|
|
; a zext of %ld.
|
|
; Currently we do not try to reuse existing extensions, so in the end we have
|
|
; 3 identical zext of %ld. The extensions will be CSE'ed by SDag.
|
|
define void @severalPromotions(ptr %addr1, ptr %addr2, i8 %a, i32 %b) {
|
|
; OPT-LABEL: define void @severalPromotions(
|
|
; OPT-SAME: ptr [[ADDR1:%.*]], ptr [[ADDR2:%.*]], i8 [[A:%.*]], i32 [[B:%.*]]) {
|
|
; OPT-NEXT: [[LD:%.*]] = load i8, ptr [[ADDR1]], align 1
|
|
; OPT-NEXT: [[PROMOTED4:%.*]] = zext i8 [[LD]] to i64
|
|
; OPT-NEXT: [[PROMOTED3:%.*]] = zext i8 [[LD]] to i64
|
|
; OPT-NEXT: [[LD2:%.*]] = load i32, ptr [[ADDR2]], align 4
|
|
; OPT-NEXT: [[SEXTADD:%.*]] = sext i32 [[LD2]] to i64
|
|
; OPT-NEXT: [[PROMOTED1:%.*]] = zext i8 [[LD]] to i64
|
|
; OPT-NEXT: [[ADD:%.*]] = add nsw i64 [[SEXTADD]], [[PROMOTED1]]
|
|
; OPT-NEXT: [[PROMOTED2:%.*]] = zext i8 [[A]] to i64
|
|
; OPT-NEXT: [[ADDZA:%.*]] = add nsw i64 [[PROMOTED2]], [[PROMOTED3]]
|
|
; OPT-NEXT: [[SEXTADDB:%.*]] = sext i32 [[B]] to i64
|
|
; OPT-NEXT: [[ADDB:%.*]] = add nsw i64 [[SEXTADDB]], [[PROMOTED4]]
|
|
; OPT-NEXT: call void @dummy(i64 [[ADD]], i64 [[ADDZA]], i64 [[ADDB]])
|
|
; OPT-NEXT: ret void
|
|
;
|
|
; DISABLE-LABEL: define void @severalPromotions(
|
|
; DISABLE-SAME: ptr [[ADDR1:%.*]], ptr [[ADDR2:%.*]], i8 [[A:%.*]], i32 [[B:%.*]]) {
|
|
; DISABLE-NEXT: [[LD:%.*]] = load i8, ptr [[ADDR1]], align 1
|
|
; DISABLE-NEXT: [[ZEXTLD:%.*]] = zext i8 [[LD]] to i32
|
|
; DISABLE-NEXT: [[LD2:%.*]] = load i32, ptr [[ADDR2]], align 4
|
|
; DISABLE-NEXT: [[ADD:%.*]] = add nsw i32 [[LD2]], [[ZEXTLD]]
|
|
; DISABLE-NEXT: [[SEXTADD:%.*]] = sext i32 [[ADD]] to i64
|
|
; DISABLE-NEXT: [[ZEXTA:%.*]] = zext i8 [[A]] to i32
|
|
; DISABLE-NEXT: [[ADDZA:%.*]] = add nsw i32 [[ZEXTA]], [[ZEXTLD]]
|
|
; DISABLE-NEXT: [[SEXTADDZA:%.*]] = sext i32 [[ADDZA]] to i64
|
|
; DISABLE-NEXT: [[ADDB:%.*]] = add nsw i32 [[B]], [[ZEXTLD]]
|
|
; DISABLE-NEXT: [[SEXTADDB:%.*]] = sext i32 [[ADDB]] to i64
|
|
; DISABLE-NEXT: call void @dummy(i64 [[SEXTADD]], i64 [[SEXTADDZA]], i64 [[SEXTADDB]])
|
|
; DISABLE-NEXT: ret void
|
|
;
|
|
%ld = load i8, ptr %addr1
|
|
%zextld = zext i8 %ld to i32
|
|
%ld2 = load i32, ptr %addr2
|
|
%add = add nsw i32 %ld2, %zextld
|
|
%sextadd = sext i32 %add to i64
|
|
%zexta = zext i8 %a to i32
|
|
%addza = add nsw i32 %zexta, %zextld
|
|
%sextaddza = sext i32 %addza to i64
|
|
%addb = add nsw i32 %b, %zextld
|
|
%sextaddb = sext i32 %addb to i64
|
|
call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
|
|
ret void
|
|
}
|
|
|
|
declare void @dummy(i64, i64, i64)
|
|
|
|
; Make sure we do not try to promote vector types since the type promotion
|
|
; helper does not support them for now.
|
|
define void @vectorPromotion() {
|
|
; OPTALL-LABEL: define void @vectorPromotion() {
|
|
; OPTALL-NEXT: entry:
|
|
; OPTALL-NEXT: [[A:%.*]] = shl nuw nsw <2 x i32> zeroinitializer, <i32 8, i32 8>
|
|
; OPTALL-NEXT: [[B:%.*]] = zext <2 x i32> [[A]] to <2 x i64>
|
|
; OPTALL-NEXT: ret void
|
|
;
|
|
entry:
|
|
%a = shl nuw nsw <2 x i32> zeroinitializer, <i32 8, i32 8>
|
|
%b = zext <2 x i32> %a to <2 x i64>
|
|
ret void
|
|
}
|
|
|
|
@a = common global i32 0, align 4
|
|
@c = common global [2 x i32] zeroinitializer, align 4
|
|
|
|
; PR21978.
|
|
; Make sure we support promotion of operands that produces a Value as opposed
|
|
; to an instruction.
|
|
; This used to cause a crash.
|
|
define i32 @promotionOfArgEndsUpInValue(ptr %addr) {
|
|
; OPT-LABEL: define i32 @promotionOfArgEndsUpInValue(
|
|
; OPT-SAME: ptr [[ADDR:%.*]]) {
|
|
; OPT-NEXT: entry:
|
|
; OPT-NEXT: [[VAL:%.*]] = load i16, ptr [[ADDR]], align 2
|
|
; OPT-NEXT: [[CONV3:%.*]] = sext i16 [[VAL]] to i32
|
|
; OPT-NEXT: [[PROMOTED1:%.*]] = zext i1 icmp ne (ptr getelementptr inbounds ([2 x i32], ptr @c, i64 0, i64 1), ptr @a) to i32
|
|
; OPT-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV3]], [[PROMOTED1]]
|
|
; OPT-NEXT: ret i32 [[ADD]]
|
|
;
|
|
; DISABLE-LABEL: define i32 @promotionOfArgEndsUpInValue(
|
|
; DISABLE-SAME: ptr [[ADDR:%.*]]) {
|
|
; DISABLE-NEXT: entry:
|
|
; DISABLE-NEXT: [[VAL:%.*]] = load i16, ptr [[ADDR]], align 2
|
|
; DISABLE-NEXT: [[EXT:%.*]] = zext i1 icmp ne (ptr getelementptr inbounds ([2 x i32], ptr @c, i64 0, i64 1), ptr @a) to i16
|
|
; DISABLE-NEXT: [[ADD:%.*]] = add nuw nsw i16 [[VAL]], [[EXT]]
|
|
; DISABLE-NEXT: [[CONV3:%.*]] = sext i16 [[ADD]] to i32
|
|
; DISABLE-NEXT: ret i32 [[CONV3]]
|
|
;
|
|
entry:
|
|
%val = load i16, ptr %addr
|
|
%ext = zext i1 icmp ne (ptr getelementptr inbounds ([2 x i32], ptr @c, i64 0, i64 1), ptr @a) to i16
|
|
%add = add nuw nsw i16 %val, %ext
|
|
%conv3 = sext i16 %add to i32
|
|
ret i32 %conv3
|
|
}
|
|
|
|
; Check that we see that one zext can be derived from the other for free.
|
|
define void @promoteTwoArgZextWithSourceExtendedTwice(ptr %p, ptr %q, i32 %b, ptr %addr) {
|
|
; OPT-LABEL: define void @promoteTwoArgZextWithSourceExtendedTwice(
|
|
; OPT-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i32 [[B:%.*]], ptr [[ADDR:%.*]]) {
|
|
; OPT-NEXT: entry:
|
|
; OPT-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
|
|
; OPT-NEXT: [[PROMOTED:%.*]] = zext i8 [[T]] to i64
|
|
; OPT-NEXT: [[ZEXTT:%.*]] = zext i8 [[T]] to i32
|
|
; OPT-NEXT: [[ADD:%.*]] = add nuw i32 [[ZEXTT]], [[B]]
|
|
; OPT-NEXT: [[ADD2:%.*]] = add nuw i64 [[PROMOTED]], 12
|
|
; OPT-NEXT: store i32 [[ADD]], ptr [[ADDR]], align 4
|
|
; OPT-NEXT: store i64 [[ADD2]], ptr [[Q]], align 8
|
|
; OPT-NEXT: ret void
|
|
;
|
|
; DISABLE-LABEL: define void @promoteTwoArgZextWithSourceExtendedTwice(
|
|
; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i32 [[B:%.*]], ptr [[ADDR:%.*]]) {
|
|
; DISABLE-NEXT: entry:
|
|
; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
|
|
; DISABLE-NEXT: [[ZEXTT:%.*]] = zext i8 [[T]] to i32
|
|
; DISABLE-NEXT: [[ADD:%.*]] = add nuw i32 [[ZEXTT]], [[B]]
|
|
; DISABLE-NEXT: [[ADD2:%.*]] = add nuw i32 [[ZEXTT]], 12
|
|
; DISABLE-NEXT: store i32 [[ADD]], ptr [[ADDR]], align 4
|
|
; DISABLE-NEXT: [[S:%.*]] = zext i32 [[ADD2]] to i64
|
|
; DISABLE-NEXT: store i64 [[S]], ptr [[Q]], align 8
|
|
; DISABLE-NEXT: ret void
|
|
;
|
|
entry:
|
|
%t = load i8, ptr %p
|
|
%zextt = zext i8 %t to i32
|
|
%add = add nuw i32 %zextt, %b
|
|
%add2 = add nuw i32 %zextt, 12
|
|
store i32 %add, ptr%addr
|
|
%s = zext i32 %add2 to i64
|
|
store i64 %s, ptr %q
|
|
ret void
|
|
}
|