Jay Foad 2754ff883d [InstCombine] Try not to demand low order bits for Add ...

Don't demand low order bits from the LHS of an Add if:
- they are not demanded in the result, and
- they are known to be zero in the RHS, so they can't possibly
  overflow and affect higher bit positions

This is intended to avoid a regression from a future patch to change
the order of canonicalization of ADD and AND.

Differential Revision: https://reviews.llvm.org/D130075

2022-08-22 20:03:53 +01:00

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