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clang-p2996/llvm/lib/Target/AMDGPU
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Stanislav Mekhanoshin febcf99e9d [AMDGPU] Replace std::pair with VOPDCombineInfo in VOPD combine. NFC. 
The future patch will carry additional info there.

Differential Revision: https://reviews.llvm.org/D152302
2023-06-06 12:53:23 -07:00
..
AsmParser
[AMDGPU][AsmParser][NFC] Refine parsing of NamedOperandU32 operands.
2023-05-29 17:01:44 +01:00
Disassembler
Split out CodeGenTypes from CodeGen for LLT/MVT
2023-05-03 00:13:20 +09:00
MCA
Split out CodeGenTypes from CodeGen for LLT/MVT
2023-05-03 00:13:20 +09:00
MCTargetDesc
[AMDGPU][AsmParser] Refine parsing of some 32-bit instruction operands.
2023-05-19 16:54:30 +01:00
TargetInfo
…
Utils
Split out CodeGenTypes from CodeGen for LLT/MVT
2023-05-03 00:13:20 +09:00
AMDGPU.h
[AMDGPU] Add pass to rewrite partially used virtual superregisters after RenameIndependentSubregs pass with registers of minimal size.
2023-05-26 09:05:44 +02:00
AMDGPU.td
AMDGPU: Expand casted f16 fmed3 pattern to fmin/fmax on gfx8
2023-05-23 08:48:25 +01:00
AMDGPUAliasAnalysis.cpp
Re-land "[AMDGPU] Define data layout entries for buffers""
2023-05-03 19:43:56 +00:00
AMDGPUAliasAnalysis.h
…
AMDGPUAlwaysInlinePass.cpp
[amdgpu] Implement dynamic LDS accesses from non-kernel functions
2023-04-04 20:06:34 +01:00
AMDGPUAnnotateKernelFeatures.cpp
…
AMDGPUAnnotateUniformValues.cpp
[AMDGPU] Replace LegacyDA with Uniformity Analysis in AnnotateUniformValues
2023-02-28 13:05:38 -07:00
AMDGPUArgumentUsageInfo.cpp
…
AMDGPUArgumentUsageInfo.h
…
AMDGPUAsmPrinter.cpp
Revert "[AMDGPU] New PAL metadata updates to ps_extra_lds_size and float_mode"
2023-06-06 13:02:28 +01:00
AMDGPUAsmPrinter.h
…
AMDGPUAtomicOptimizer.cpp
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
AMDGPUAttributes.def
…
AMDGPUAttributor.cpp
…
AMDGPUCallingConv.td
…
AMDGPUCallLowering.cpp
[CodeGen] Replace CCState's getNextStackOffset with getStackSize (NFC)
2023-05-17 21:51:45 +03:00
AMDGPUCallLowering.h
…
AMDGPUCodeGenPrepare.cpp
[AMDGPUCodegenPrepare] Add NewPM Support
2023-05-26 00:20:01 -06:00
AMDGPUCombine.td
AMDGPU: Expand casted f16 fmed3 pattern to fmin/fmax on gfx8
2023-05-23 08:48:25 +01:00
AMDGPUCombinerHelper.cpp
AMDGPU: Expand casted f16 fmed3 pattern to fmin/fmax on gfx8
2023-05-23 08:48:25 +01:00
AMDGPUCombinerHelper.h
AMDGPU: Expand casted f16 fmed3 pattern to fmin/fmax on gfx8
2023-05-23 08:48:25 +01:00
AMDGPUCtorDtorLowering.cpp
[AMDGPU] Add attribute to AMDGPU ctor / dtor to indicate single threadedness
2023-05-24 07:24:17 -05:00
AMDGPUCtorDtorLowering.h
…
AMDGPUExportClustering.cpp
…
AMDGPUExportClustering.h
…
AMDGPUFeatures.td
…
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUGenRegisterBankInfo.def
…
AMDGPUGISel.td
[AMDGPU] Move V_FMA_MIX pattern matching into tablegen. NFC
2023-02-23 10:23:34 -08:00
AMDGPUGlobalISelUtils.cpp
Restore CodeGen/LowLevelType from Support
2023-05-03 00:13:19 +09:00
AMDGPUGlobalISelUtils.h
…
AMDGPUHSAMetadataStreamer.cpp
AMDGPU: Really invert handling of enqueued block detection
2023-04-20 06:58:24 -04:00
AMDGPUHSAMetadataStreamer.h
…
AMDGPUIGroupLP.cpp
[AMDGPU][IGLP] Parameterize the SchedGroup processing / linking order in Solver
2023-05-30 14:43:14 -07:00
AMDGPUIGroupLP.h
…
AMDGPUInsertDelayAlu.cpp
[AMDGPU] More precise limit on SALU cycles in s_delay_alu instructions
2023-03-05 08:14:15 +00:00
AMDGPUInstCombineIntrinsic.cpp
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
AMDGPUInstrInfo.cpp
…
AMDGPUInstrInfo.h
…
AMDGPUInstrInfo.td
AMDGPU: Define sub-class of SGPR_64 for tail call return
2023-04-27 10:45:11 -07:00
AMDGPUInstructions.td
AMDGPU: Fold zext into result of v_mad_u16 on high zeroing targets
2023-06-05 18:41:07 -04:00
AMDGPUInstructionSelector.cpp
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
AMDGPUInstructionSelector.h
[AMDGPU][GISel] Add inverse ballot intrinsic
2023-04-06 07:46:50 +02:00
AMDGPUISelDAGToDAG.cpp
[SelectionDAG] Rename ADDCARRY/SUBCARRY to UADDO_CARRY/USUBO_CARRY (NFC)
2023-04-29 21:59:58 +03:00
AMDGPUISelDAGToDAG.h
[llvm] Use llvm::isNullConstant (NFC)
2023-03-22 00:31:48 -07:00
AMDGPUISelLowering.cpp
[AMDGPU] Remove extract_subvector patterns
2023-06-06 14:04:50 +01:00
AMDGPUISelLowering.h
[AMDGPU] Improve abs modifier usage
2023-05-19 12:02:21 +02:00
AMDGPULateCodeGenPrepare.cpp
AMDGPU: Use getTypeStoreSizeInBits
2023-04-29 10:35:06 -04:00
AMDGPULegalizerInfo.cpp
[AMDGPU] Add intrinsic for converting global pointers to resources
2023-06-05 17:07:59 +00:00
AMDGPULegalizerInfo.h
[AMDGPU] Add intrinsic for converting global pointers to resources
2023-06-05 17:07:59 +00:00
AMDGPULibCalls.cpp
…
AMDGPULibFunc.cpp
…
AMDGPULibFunc.h
…
AMDGPULowerIntrinsics.cpp
…
AMDGPULowerKernelArguments.cpp
AMDGPU: Don't need pointer bitcast in AMDGPULowerKernelArguments
2023-04-29 15:11:31 -04:00
AMDGPULowerKernelAttributes.cpp
…
AMDGPULowerModuleLDSPass.cpp
[amdgpu][nfc] Update comments on LDS lowering
2023-04-11 10:48:19 +01:00
AMDGPUMachineCFGStructurizer.cpp
…
AMDGPUMachineFunction.cpp
[amdgpu] Implement dynamic LDS accesses from non-kernel functions
2023-04-04 20:06:34 +01:00
AMDGPUMachineFunction.h
[amdgpu] Implement dynamic LDS accesses from non-kernel functions
2023-04-04 20:06:34 +01:00
AMDGPUMachineModuleInfo.cpp
…
AMDGPUMachineModuleInfo.h
…
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
…
AMDGPUMCInstLower.cpp
AMDGPU: Define sub-class of SGPR_64 for tail call return
2023-04-27 10:45:11 -07:00
AMDGPUMCInstLower.h
…
AMDGPUMIRFormatter.cpp
…
AMDGPUMIRFormatter.h
…
AMDGPUOpenCLEnqueuedBlockLowering.cpp
AMDGPU: Really invert handling of enqueued block detection
2023-04-20 06:58:24 -04:00
AMDGPUPerfHintAnalysis.cpp
…
AMDGPUPerfHintAnalysis.h
…
AMDGPUPostLegalizerCombiner.cpp
[AMDGPU] Improve the lowering of raw_buffer_load_{i8,i16} and struct_buffer_load_{i8,i16} intrinsics
2023-02-22 09:01:33 -08:00
AMDGPUPreLegalizerCombiner.cpp
…
AMDGPUPrintfRuntimeBinding.cpp
…
AMDGPUPromoteAlloca.cpp
[AMDGPU] Reintroduce CC exception for non-inlined functions in Promote Alloca limits
2023-05-23 09:01:39 +02:00
AMDGPUPromoteKernelArguments.cpp
…
AMDGPUPropagateAttributes.cpp
…
AMDGPUPTNote.h
…
AMDGPURegBankCombiner.cpp
AMDGPU: Expand casted f16 fmed3 pattern to fmin/fmax on gfx8
2023-05-23 08:48:25 +01:00
AMDGPURegBankSelect.cpp
…
AMDGPURegBankSelect.h
…
AMDGPURegisterBankInfo.cpp
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
AMDGPURegisterBankInfo.h
[LLVM][Uniformity] Improve detection of uniform registers
2023-05-16 09:37:04 +05:30
AMDGPURegisterBanks.td
…
AMDGPUReleaseVGPRs.cpp
…
AMDGPURemoveIncompatibleFunctions.cpp
[AMDGPU] Remove function if FeatureWavefrontSize 32 is not supported on current GPU
2023-05-19 23:49:01 +05:30
AMDGPUResourceUsageAnalysis.cpp
[AMDGPU] Do not crash on agpr_hi16 in AMDGPUResourceUsageAnalysis
2023-04-18 13:53:01 +02:00
AMDGPUResourceUsageAnalysis.h
…
AMDGPURewriteOutArguments.cpp
AMDGPU: Don't need pointer bitcasts in AMDGPURewriteOutArguments
2023-04-29 10:35:06 -04:00
AMDGPURewriteUndefForPHI.cpp
[AMDGPU] Use UniformityAnalysis in RewriteUndefsForPHI
2023-03-06 12:15:33 +01:00
AMDGPUSearchableTables.td
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
AMDGPUSetWavePriority.cpp
…
AMDGPUSubtarget.cpp
…
AMDGPUSubtarget.h
…
AMDGPUTargetMachine.cpp
[AMDGPU] Add pass to rewrite partially used virtual superregisters after RenameIndependentSubregs pass with registers of minimal size.
2023-05-26 09:05:44 +02:00
AMDGPUTargetMachine.h
…
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
Don't disable loop unroll for vectorized loops on AMDGPU target
2023-05-25 22:54:41 +02:00
AMDGPUTargetTransformInfo.h
[NFC][TargetTransformInfo] Make getInliningThreholdMultiplier and getInlinerVectorBonusPercent const
2023-06-01 17:09:01 +02:00
AMDGPUUnifyDivergentExitNodes.cpp
Revert "[AMDGPU][NFC] Preserve PDTWrapperPass in UnifyDivergentExitNodes"
2023-05-03 09:34:55 -06:00
AMDGPUUnifyDivergentExitNodes.h
[AMDGPUUnifyDivergentExitNodes] Add NewPM support
2023-03-25 14:04:36 -06:00
AMDGPUUnifyMetadata.cpp
…
AMDKernelCodeT.h
…
BUFInstructions.td
[AMDGPU] Create Subtarget Features for some of 16 bits atomic fadd instructions
2023-03-24 13:10:40 +01:00
CaymanInstructions.td
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CMakeLists.txt
[AMDGPU] Add pass to rewrite partially used virtual superregisters after RenameIndependentSubregs pass with registers of minimal size.
2023-05-26 09:05:44 +02:00
DSInstructions.td
[AMDGPU] TableGen syntax cleanups
2023-03-30 11:45:50 +01:00
EvergreenInstructions.td
…
EXPInstructions.td
…
FLATInstructions.td
[AMDGPU] Consistently use v2i16 for packed bf16 inputs. NFC.
2023-03-29 20:23:36 +01:00
GCNCreateVOPD.cpp
[AMDGPU] Replace std::pair with VOPDCombineInfo in VOPD combine. NFC.
2023-06-06 12:53:23 -07:00
GCNDPPCombine.cpp
…
GCNHazardRecognizer.cpp
[AMDGPU] Fix odd implicit operand handling in clause breaking
2023-05-19 21:24:33 +01:00
GCNHazardRecognizer.h
…
GCNILPSched.cpp
…
GCNIterativeScheduler.cpp
[AMDGPU] Make use of MachineInstr::all_defs and all_uses. NFCI.
2023-06-05 10:32:33 +01:00
GCNIterativeScheduler.h
…
GCNMinRegStrategy.cpp
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GCNNSAReassign.cpp
[AMDGPU] Make use of GCNSubtarget::hasNSAEncoding. NFC.
2023-03-21 10:00:56 +00:00
GCNPreRAOptimizations.cpp
…
GCNProcessors.td
AMDGPU: Add basic gfx942 target
2023-05-10 11:51:06 -04:00
GCNRegPressure.cpp
[AMDGPU] Make use of MachineInstr::all_defs and all_uses. NFCI.
2023-06-05 10:32:33 +01:00
GCNRegPressure.h
…
GCNRewritePartialRegUses.cpp
[AMDGPU] Add pass to rewrite partially used virtual superregisters after RenameIndependentSubregs pass with registers of minimal size.
2023-05-26 09:05:44 +02:00
GCNSchedStrategy.cpp
[AMDGPU] Make use of MachineInstr::all_defs and all_uses. NFCI.
2023-06-05 10:32:33 +01:00
GCNSchedStrategy.h
…
GCNSubtarget.h
AMDGPU: Force sc0 and sc1 on stores for gfx940 and gfx941
2023-05-12 11:53:19 -04:00
GCNVOPDUtils.cpp
…
GCNVOPDUtils.h
…
InstCombineTables.td
…
LDSDIRInstructions.td
…
MIMGInstructions.td
[AMDGPU] Make use of new tablegen operator !range. NFC.
2023-05-02 10:36:15 +01:00
R600.h
…
R600.td
…
R600AsmPrinter.cpp
…
R600AsmPrinter.h
…
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
…
R600Defines.h
…
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
…
R600FrameLowering.cpp
…
R600FrameLowering.h
…
R600InstrFormats.td
…
R600InstrInfo.cpp
[Target] Use *{Set,Map}::contains (NFC)
2023-03-14 18:06:55 -07:00
R600InstrInfo.h
…
R600InstrInfo.td
…
R600Instructions.td
…
R600ISelDAGToDAG.cpp
…
R600ISelLowering.cpp
[llvm] Use llvm::isNullConstant (NFC)
2023-03-22 00:31:48 -07:00
R600ISelLowering.h
…
R600MachineCFGStructurizer.cpp
…
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
…
R600MachineScheduler.h
…
R600MCInstLower.cpp
…
R600OpenCLImageTypeLoweringPass.cpp
…
R600OptimizeVectorRegisters.cpp
…
R600Packetizer.cpp
…
R600Processors.td
…
R600RegisterInfo.cpp
…
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600Subtarget.cpp
…
R600Subtarget.h
…
R600TargetMachine.cpp
…
R600TargetMachine.h
…
R600TargetTransformInfo.cpp
[LV][NFC] Use ElementCount for getMaxInterleaveFactor
2023-02-22 10:15:05 +00:00
R600TargetTransformInfo.h
[LV][NFC] Use ElementCount for getMaxInterleaveFactor
2023-02-22 10:15:05 +00:00
R700Instructions.td
…
SIAnnotateControlFlow.cpp
[SIAnnotateControlFlow] Use Uniformity analysis
2023-03-01 10:19:45 -07:00
SIDefines.h
[AMDGPU] Add pass to rewrite partially used virtual superregisters after RenameIndependentSubregs pass with registers of minimal size.
2023-05-26 09:05:44 +02:00
SIFixSGPRCopies.cpp
[AMDGPU] Introduce SIInstrWorklist to process instructions in moveToVALU
2023-04-10 11:34:14 +05:30
SIFixVGPRCopies.cpp
…
SIFoldOperands.cpp
[AMDGPU] Fold more AGPR copies/PHIs in SIFoldOperands
2023-03-28 09:33:12 +02:00
SIFormMemoryClauses.cpp
[AMDGPU] Make use of MachineInstr::all_defs and all_uses. NFCI.
2023-06-05 10:32:33 +01:00
SIFrameLowering.cpp
[AMDGPU] Check if register is non-null before calling isSubRegisterEq (NFCI)
2023-05-24 10:32:07 +03:00
SIFrameLowering.h
…
SIInsertHardClauses.cpp
…
SIInsertWaitcnts.cpp
[AMDGPU] Don't flush vmcnt for loops with use/def pairs
2023-06-02 22:55:12 -07:00
SIInstrFormats.td
…
SIInstrInfo.cpp
[AMDGPU] Make use of MachineInstr::all_defs and all_uses. NFCI.
2023-06-05 10:32:33 +01:00
SIInstrInfo.h
[AMDGPU] Add missing whitespace in SIInstrInfo header (NFC)
2023-05-17 16:23:10 +09:00
SIInstrInfo.td
[AMDGPU][AsmParser][NFC] Specify parser methods directly in operand classes.
2023-06-05 13:04:15 +01:00
SIInstructions.td
[AMDGPU] Remove extract_subvector patterns
2023-06-06 14:04:50 +01:00
SIISelLowering.cpp
[AMDGPU] Add intrinsic for converting global pointers to resources
2023-06-05 17:07:59 +00:00
SIISelLowering.h
[AMDGPU] Add intrinsic for converting global pointers to resources
2023-06-05 17:07:59 +00:00
SILateBranchLowering.cpp
…
SILoadStoreOptimizer.cpp
[AMDGPU] Do not handle _SGPR SMEM instructions in SILoadStoreOptimizer
2023-04-25 15:40:13 +01:00
SILowerControlFlow.cpp
[AMDGPU] Make use of MachineInstr::all_defs and all_uses. NFCI.
2023-06-05 10:32:33 +01:00
SILowerI1Copies.cpp
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SILowerSGPRSpills.cpp
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SIMachineFunctionInfo.cpp
AMDGPU: Fix missing MIR serialization for PSInputAddr/PSInputEnable
2023-04-08 07:05:35 -04:00
SIMachineFunctionInfo.h
[AMDGPU] Fix warnings
2023-05-19 10:56:23 -07:00
SIMachineScheduler.cpp
[MachineScheduler] Rename postprocessDAG to postProcessDAG. NFC
2023-03-30 10:47:20 +08:00
SIMachineScheduler.h
…
SIMemoryLegalizer.cpp
AMDGPU: Force sc0 and sc1 on stores for gfx940 and gfx941
2023-05-12 11:53:19 -04:00
SIModeRegister.cpp
[AMDGPU] Modernize Status and BlockData (NFC)
2023-04-16 13:03:02 -07:00
SIModeRegisterDefaults.cpp
[AMDGPU] Split SIModeRegisterDefaults out of AMDGPUBaseInfo. NFC.
2023-02-23 16:38:15 +00:00
SIModeRegisterDefaults.h
LangRef: Add "dynamic" option to "denormal-fp-math"
2023-04-29 08:44:59 -04:00
SIOptimizeExecMasking.cpp
…
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU] Recompute liveness in SIOptimizeExecMaskingPreRA
2023-05-09 09:02:22 +02:00
SIOptimizeVGPRLiveRange.cpp
[AMDGPU] Make use of MachineInstr::all_defs and all_uses. NFCI.
2023-06-05 10:32:33 +01:00
SIPeepholeSDWA.cpp
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SIPostRABundler.cpp
…
SIPreAllocateWWMRegs.cpp
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SIPreEmitPeephole.cpp
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SIProgramInfo.cpp
[AMDGPU] Add backend support for new PAL ELF Metadata 3.0
2023-04-14 09:57:13 +01:00
SIProgramInfo.h
[AMDGPU] Add backend support for new PAL ELF Metadata 3.0
2023-04-14 09:57:13 +01:00
SIRegisterInfo.cpp
[AMDGPU] Add pass to rewrite partially used virtual superregisters after RenameIndependentSubregs pass with registers of minimal size.
2023-05-26 09:05:44 +02:00
SIRegisterInfo.h
[AMDGPU] Add pass to rewrite partially used virtual superregisters after RenameIndependentSubregs pass with registers of minimal size.
2023-05-26 09:05:44 +02:00
SIRegisterInfo.td
[AMDGPU] 4-align SGPR triples
2023-05-26 08:06:25 +01:00
SISchedule.td
…
SIShrinkInstructions.cpp
[AMDGPU][GFX11] Legalize and select partial NSA MIMG instructions
2023-02-23 13:33:34 +01:00
SIWholeQuadMode.cpp
[AMDGPU] WQM: Ensure exact mode placement before branches
2023-06-06 18:11:35 +09:00
SMInstructions.td
[AMDGPU][AsmParser][NFC] Refine parsing of NamedOperandU32 operands.
2023-05-29 17:01:44 +01:00
SOPInstructions.td
…
VIInstrFormats.td
…
VINTERPInstructions.td
…
VOP1Instructions.td
[AMDGPU] Remove BoolToList class
2023-03-13 09:22:52 +00:00
VOP2Instructions.td
[AMDGPU][Uniformity] V_MBCNT* is never uniform
2023-05-18 13:50:12 +09:00
VOP3Instructions.td
AMDGPU: Fold zext into result of v_mad_u16 on high zeroing targets
2023-06-05 18:41:07 -04:00
VOP3PInstructions.td
[AMDGPU] Remove BoolToList class
2023-03-13 09:22:52 +00:00
VOPCInstructions.td
[AMDGPU] Remove BoolToList class
2023-03-13 09:22:52 +00:00
VOPDInstructions.td
…
VOPInstructions.td
[AMDGPU] Remove BoolToList class
2023-03-13 09:22:52 +00:00