David Green 146d44c251 [LSR] Don't require register reuse under postinc ...

LSR has some logic that tries to aggressively reuse registers in
formula. This can lead to sub-optimal decision in complex loops where
the backend it trying to use shouldFavorPostInc. This disables the
re-use in those situations.

Differential Revision: https://reviews.llvm.org/D79301

2020-05-05 16:04:50 +01:00

..

AArch64

[AArch64][SVE] Guard bitcast patterns under IsLE predicate

2020-05-05 13:18:35 +01:00

AMDGPU

[AMDGPU] Better support for VMEM soft clauses in GCNHazardRecognizer

2020-05-05 15:49:09 +01:00

ARC

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ARM

[ARM] Fix tail call validity checking for varargs calls.

2020-05-04 12:34:14 -07:00

AVR

[AVR] Do not place functions in .progmem.data

2020-04-20 13:56:38 +02:00

BPF

BPF: fix a CORE optimization bug

2020-04-20 19:54:51 -07:00

Generic

[MachineDebugify] Insert synthetic DBG_VALUE instructions

2020-04-22 17:03:39 -07:00

Hexagon

[RegisterCoalescer] Extend a subrange if needed when filling range gap

2020-05-04 16:49:59 -05:00

Inputs

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Lanai

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Mips

[SelectionDAGBuilder] Stop setting alignment to one for hidden sret values

2020-05-04 14:44:39 +01:00

MIR

[AMDGPU] Avoid hard-coded line numbers in error message checks

2020-04-23 21:06:09 +01:00

MSP430

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NVPTX

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PowerPC

[PowerPC][AIX][NFC] Remove spills and reloads from arg passing test.

2020-05-04 14:26:33 -04:00

RISCV

[RISCV] Implement convertSelectOfConstantsToMath

2020-05-02 15:05:57 +01:00

SPARC

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SystemZ

[SystemZ] Fix test case.

2020-04-28 09:43:03 +02:00

Thumb

[ARM] Don't shrink STM if it would cause an unknown base register store

2020-04-22 14:50:42 +01:00

Thumb2

[LSR] Don't require register reuse under postinc

2020-05-05 16:04:50 +01:00

VE

[VE] Update branch instructions

2020-04-28 09:41:01 +02:00

WebAssembly

[WebAssembly] Fix block marker placing after fixUnwindMismatches

2020-05-05 02:06:47 -07:00

WinCFGuard

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WinEH

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X86

[X86][AVX] combineVectorSignBitsTruncation - avoid complex vXi64->vXi32 PACKSS truncations (PR45794)

2020-05-05 11:57:25 +01:00

XCore

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