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clang-p2996/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
Craig Topper 3bcb1f2bdd [RISCV] Rework isSignExtendingOpW to store Register in the worklist. 
Previously we stored MachineInstr which restricted the implementation
to only handle operand 0.

The TH_LWD instruction has two sign extended destinations.
2024-02-03 23:40:09 -08:00

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