clang-p2996

custom-pseudo-source-values.ll

[AMDGPU] Use resource base for buffer instruction MachineMemOperands

2023-06-05 17:06:57 +00:00

dead-flag-on-use-operand-parse-error.mir

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empty-custom-regmask.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

expected-target-index-name.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

intrinsics.mir

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invalid-frame-index2.mir

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invalid-frame-index-invalid-fixed-stack.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index-invalid-stack.mir

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invalid-frame-index-no-stack.mir

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invalid-frame-index.mir

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invalid-target-index-operand.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

killed-flag-on-def-parse-error.mir

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lit.local.cfg

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llc-target-cpu-attr-from-cmdline-ir.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

llc-target-cpu-attr-from-cmdline.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

long-branch-reg-all-sgpr-used.ll

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

machine-function-info-after-pei.ll

[AMDGPU] Add IsChainFunction to the MachineFunctionInfo

2023-08-21 12:37:32 +02:00

machine-function-info-dynlds-align-invalid-case.mir

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machine-function-info-long-branch-reg-debug.ll

[AMDGPU] Add IsChainFunction to the MachineFunctionInfo

2023-08-21 12:37:32 +02:00

machine-function-info-long-branch-reg.ll

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machine-function-info-no-ir.mir

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machine-function-info-register-parse-error1.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

machine-function-info-register-parse-error2.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

machine-function-info.ll

[AMDGPU] Add IsChainFunction to the MachineFunctionInfo

2023-08-21 12:37:32 +02:00

machine-metadata-error.mir

[MIRParser] Add machine metadata.

2021-06-28 22:29:36 -04:00

machine-metadata.mir

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mfi-frame-offset-reg-class.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

mfi-parse-error-frame-offset-reg.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

mfi-parse-error-scratch-rsrc-reg.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

mfi-parse-error-stack-ptr-offset-reg.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

mfi-scratch-rsrc-reg-reg-class.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

mfi-stack-ptr-offset-reg-class.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

mir-canon-multi.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

mircanon-memoperands.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

noconvergent-invalid.mir

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noconvergent.mir

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parse-order-reserved-regs.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

sgpr-for-exec-copy-invalid-reg.mir

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stack-id-assert.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

stack-id.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

subreg-def-is-not-ssa.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

syncscopes.mir

[AMDGPU] Change syncscopes.mir not to use undefined cpol bits. NFC.

2023-08-04 11:19:12 -07:00

target-flags.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

target-index-operands.mir

[AMDGPU,test] Change llc -march= to -mtriple= (#75982 )

2024-01-16 21:54:58 -08:00

target-memoperands.mir

[AMDGPU] Add mark last scratch load pass (#75512 )

2024-01-18 09:36:44 +01:00

vgpr-for-agpr-copy-invalid-reg.mir

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virtreg-uses-unallocatable-class.mir

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wwm-reserved-regs-invalid-reg.mir

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wwm-reserved-regs-not-a-reg.mir

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wwm-reserved-regs.mir

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