The s_singleuse_vdst instruction is used to mark regions of instructions that produce values that have only one use. Certain instructions take more than one cycle to execute, resulting in regions being incorrectly marked. This patch excludes these multi-cycle instructions from being marked as either producing single use values or consuming single use values or both depending on the instruction.
246 lines
8.7 KiB
C++
246 lines
8.7 KiB
C++
//===- AMDGPUInsertSingleUseVDST.cpp - Insert s_singleuse_vdst instructions ==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Insert s_singleuse_vdst instructions on GFX11.5+ to mark regions of VALU
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/// instructions that produce single-use VGPR values. If the value is forwarded
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/// to the consumer instruction prior to VGPR writeback, the hardware can
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/// then skip (kill) the VGPR write.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUGenSearchableTables.inc"
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#include "GCNSubtarget.h"
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#include "SIInstrInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/MC/MCRegister.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Pass.h"
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#include <array>
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using namespace llvm;
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#define DEBUG_TYPE "amdgpu-insert-single-use-vdst"
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namespace {
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class AMDGPUInsertSingleUseVDST : public MachineFunctionPass {
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private:
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const SIInstrInfo *SII;
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class SingleUseInstruction {
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private:
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static const unsigned MaxSkipRange = 0b111;
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static const unsigned MaxNumberOfSkipRegions = 2;
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unsigned LastEncodedPositionEnd;
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MachineInstr *ProducerInstr;
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std::array<unsigned, MaxNumberOfSkipRegions + 1> SingleUseRegions;
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SmallVector<unsigned, MaxNumberOfSkipRegions> SkipRegions;
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// Adds a skip region into the instruction.
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void skip(const unsigned ProducerPosition) {
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while (LastEncodedPositionEnd + MaxSkipRange < ProducerPosition) {
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SkipRegions.push_back(MaxSkipRange);
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LastEncodedPositionEnd += MaxSkipRange;
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}
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SkipRegions.push_back(ProducerPosition - LastEncodedPositionEnd);
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LastEncodedPositionEnd = ProducerPosition;
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}
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bool currentRegionHasSpace() {
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const auto Region = SkipRegions.size();
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// The first region has an extra bit of encoding space.
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return SingleUseRegions[Region] <
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((Region == MaxNumberOfSkipRegions) ? 0b1111U : 0b111U);
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}
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unsigned encodeImm() {
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// Handle the first Single Use Region separately as it has an extra bit
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// of encoding space.
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unsigned Imm = SingleUseRegions[SkipRegions.size()];
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unsigned ShiftAmount = 4;
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for (unsigned i = SkipRegions.size(); i > 0; i--) {
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Imm |= SkipRegions[i - 1] << ShiftAmount;
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ShiftAmount += 3;
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Imm |= SingleUseRegions[i - 1] << ShiftAmount;
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ShiftAmount += 3;
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}
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return Imm;
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}
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public:
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SingleUseInstruction(const unsigned ProducerPosition,
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MachineInstr *Producer)
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: LastEncodedPositionEnd(ProducerPosition + 1), ProducerInstr(Producer),
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SingleUseRegions({1, 0, 0}) {}
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// Returns false if adding a new single use producer failed. This happens
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// because it could not be encoded, either because there is no room to
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// encode another single use producer region or that this single use
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// producer is too far away to encode the amount of instructions to skip.
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bool tryAddProducer(const unsigned ProducerPosition, MachineInstr *MI) {
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// Producer is too far away to encode into this instruction or another
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// skip region is needed and SkipRegions.size() = 2 so there's no room for
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// another skip region, therefore a new instruction is needed.
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if (LastEncodedPositionEnd +
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(MaxSkipRange * (MaxNumberOfSkipRegions - SkipRegions.size())) <
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ProducerPosition)
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return false;
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// If a skip region is needed.
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if (LastEncodedPositionEnd != ProducerPosition ||
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!currentRegionHasSpace()) {
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// If the current region is out of space therefore a skip region would
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// be needed, but there is no room for another skip region.
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if (SkipRegions.size() == MaxNumberOfSkipRegions)
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return false;
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skip(ProducerPosition);
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}
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SingleUseRegions[SkipRegions.size()]++;
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LastEncodedPositionEnd = ProducerPosition + 1;
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ProducerInstr = MI;
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return true;
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}
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auto emit(const SIInstrInfo *SII) {
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return BuildMI(*ProducerInstr->getParent(), ProducerInstr, DebugLoc(),
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SII->get(AMDGPU::S_SINGLEUSE_VDST))
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.addImm(encodeImm());
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}
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};
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public:
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static char ID;
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AMDGPUInsertSingleUseVDST() : MachineFunctionPass(ID) {}
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void insertSingleUseInstructions(
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ArrayRef<std::pair<unsigned, MachineInstr *>> SingleUseProducers) const {
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SmallVector<SingleUseInstruction> Instructions;
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for (auto &[Position, MI] : SingleUseProducers) {
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// Encode this position into the last single use instruction if possible.
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if (Instructions.empty() ||
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!Instructions.back().tryAddProducer(Position, MI)) {
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// If not, add a new instruction.
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Instructions.push_back(SingleUseInstruction(Position, MI));
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}
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}
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for (auto &Instruction : Instructions)
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Instruction.emit(SII);
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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const auto &ST = MF.getSubtarget<GCNSubtarget>();
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if (!ST.hasVGPRSingleUseHintInsts())
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return false;
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SII = ST.getInstrInfo();
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const auto *TRI = &SII->getRegisterInfo();
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bool InstructionEmitted = false;
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for (MachineBasicBlock &MBB : MF) {
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DenseMap<MCRegUnit, unsigned> RegisterUseCount;
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// Handle boundaries at the end of basic block separately to avoid
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// false positives. If they are live at the end of a basic block then
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// assume it has more uses later on.
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for (const auto &Liveout : MBB.liveouts()) {
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for (MCRegUnitMaskIterator Units(Liveout.PhysReg, TRI); Units.isValid();
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++Units) {
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const auto [Unit, Mask] = *Units;
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if ((Mask & Liveout.LaneMask).any())
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RegisterUseCount[Unit] = 2;
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}
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}
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SmallVector<std::pair<unsigned, MachineInstr *>>
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SingleUseProducerPositions;
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unsigned VALUInstrCount = 0;
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for (MachineInstr &MI : reverse(MBB.instrs())) {
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// All registers in all operands need to be single use for an
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// instruction to be marked as a single use producer.
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bool AllProducerOperandsAreSingleUse = true;
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// Gather a list of Registers used before updating use counts to avoid
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// double counting registers that appear multiple times in a single
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// MachineInstr.
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SmallVector<MCRegUnit> RegistersUsed;
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for (const auto &Operand : MI.all_defs()) {
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const auto Reg = Operand.getReg();
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const auto RegUnits = TRI->regunits(Reg);
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if (any_of(RegUnits, [&RegisterUseCount](const MCRegUnit Unit) {
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return RegisterUseCount[Unit] > 1;
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}))
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AllProducerOperandsAreSingleUse = false;
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// Reset uses count when a register is no longer live.
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for (const MCRegUnit Unit : RegUnits)
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RegisterUseCount.erase(Unit);
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}
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for (const auto &Operand : MI.all_uses()) {
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const auto Reg = Operand.getReg();
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// Count the number of times each register is read.
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for (const MCRegUnit Unit : TRI->regunits(Reg)) {
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if (!is_contained(RegistersUsed, Unit))
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RegistersUsed.push_back(Unit);
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}
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}
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for (const MCRegUnit Unit : RegistersUsed)
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RegisterUseCount[Unit]++;
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// Do not attempt to optimise across exec mask changes.
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if (MI.modifiesRegister(AMDGPU::EXEC, TRI) ||
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AMDGPU::isInvalidSingleUseConsumerInst(MI.getOpcode())) {
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for (auto &UsedReg : RegisterUseCount)
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UsedReg.second = 2;
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}
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if (!SIInstrInfo::isVALU(MI) ||
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AMDGPU::isInvalidSingleUseProducerInst(MI.getOpcode()))
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continue;
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if (AllProducerOperandsAreSingleUse) {
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SingleUseProducerPositions.push_back({VALUInstrCount, &MI});
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InstructionEmitted = true;
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}
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VALUInstrCount++;
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}
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insertSingleUseInstructions(SingleUseProducerPositions);
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}
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return InstructionEmitted;
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}
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};
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} // namespace
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char AMDGPUInsertSingleUseVDST::ID = 0;
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char &llvm::AMDGPUInsertSingleUseVDSTID = AMDGPUInsertSingleUseVDST::ID;
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INITIALIZE_PASS(AMDGPUInsertSingleUseVDST, DEBUG_TYPE,
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"AMDGPU Insert SingleUseVDST", false, false)
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