6599961c17
This patch contains following enhancements to SrcRegMap and DstRegMap:
1 In findOnlyInterestingUse not only check if the Reg is two address usage,
but also check after commutation can it be two address usage.
2 If a physical register is clobbered, remove SrcRegMap entries that are
mapped to it.
3 In processTiedPairs, when create a new COPY instruction, add a SrcRegMap
entry only when the COPY instruction is coalescable. (The COPY src is
killed)
With these enhancements isProfitableToCommute can do better commute decision,
and finally more register copies are removed.
Differential Revision: https://reviews.llvm.org/D108731
151 lines
5.1 KiB
LLVM
151 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=CHECK64
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; Check a few invalid patterns for halfword bswap pattern matching
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; Don't match a near-miss 32-bit packed halfword bswap
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; (with only half of the swap tree valid).
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define i32 @test1(i32 %x) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: andl $16711680, %ecx # imm = 0xFF0000
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: orl $-16777216, %edx # imm = 0xFF000000
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; CHECK-NEXT: shll $8, %ecx
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; CHECK-NEXT: shrl $8, %edx
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; CHECK-NEXT: orl %ecx, %edx
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; CHECK-NEXT: bswapl %eax
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; CHECK-NEXT: shrl $16, %eax
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; CHECK-NEXT: orl %edx, %eax
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; CHECK-NEXT: retl
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;
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; CHECK64-LABEL: test1:
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; CHECK64: # %bb.0:
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; CHECK64-NEXT: movl %edi, %ecx
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; CHECK64-NEXT: andl $16711680, %ecx # imm = 0xFF0000
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; CHECK64-NEXT: movl %edi, %eax
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; CHECK64-NEXT: orl $-16777216, %eax # imm = 0xFF000000
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; CHECK64-NEXT: shll $8, %ecx
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; CHECK64-NEXT: shrl $8, %eax
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; CHECK64-NEXT: orl %ecx, %eax
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; CHECK64-NEXT: bswapl %edi
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; CHECK64-NEXT: shrl $16, %edi
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; CHECK64-NEXT: orl %edi, %eax
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; CHECK64-NEXT: retq
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%byte0 = and i32 %x, 255 ; 0x000000ff
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%byte1 = and i32 %x, 65280 ; 0x0000ff00
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%byte2 = and i32 %x, 16711680 ; 0x00ff0000
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%byte3 = or i32 %x, 4278190080 ; 0xff000000
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%tmp0 = shl i32 %byte0, 8
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%tmp1 = lshr i32 %byte1, 8
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%tmp2 = shl i32 %byte2, 8
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%tmp3 = lshr i32 %byte3, 8
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%or0 = or i32 %tmp0, %tmp1
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%or1 = or i32 %tmp2, %tmp3
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%result = or i32 %or0, %or1
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ret i32 %result
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}
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; Don't match a near-miss 32-bit packed halfword bswap
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; (with swapped lshr/shl)
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; ((x >> 8) & 0x0000ff00) |
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; ((x << 8) & 0x000000ff) |
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; ((x << 8) & 0xff000000) |
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; ((x >> 8) & 0x00ff0000)
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define i32 @test2(i32 %x) nounwind {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: shrl $8, %eax
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; CHECK-NEXT: shll $8, %ecx
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: andl $65280, %edx # imm = 0xFF00
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; CHECK-NEXT: andl $-16777216, %ecx # imm = 0xFF000000
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; CHECK-NEXT: andl $16711680, %eax # imm = 0xFF0000
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: orl %edx, %eax
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; CHECK-NEXT: retl
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;
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; CHECK64-LABEL: test2:
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; CHECK64: # %bb.0:
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; CHECK64-NEXT: movl %edi, %eax
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; CHECK64-NEXT: shrl $8, %eax
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; CHECK64-NEXT: shll $8, %edi
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; CHECK64-NEXT: movl %eax, %ecx
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; CHECK64-NEXT: andl $65280, %ecx # imm = 0xFF00
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; CHECK64-NEXT: andl $-16777216, %edi # imm = 0xFF000000
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; CHECK64-NEXT: andl $16711680, %eax # imm = 0xFF0000
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; CHECK64-NEXT: orl %edi, %eax
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; CHECK64-NEXT: orl %ecx, %eax
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; CHECK64-NEXT: retq
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%byte1 = lshr i32 %x, 8
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%byte0 = shl i32 %x, 8
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%byte3 = shl i32 %x, 8
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%byte2 = lshr i32 %x, 8
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%tmp1 = and i32 %byte1, 65280 ; 0x0000ff00
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%tmp0 = and i32 %byte0, 255 ; 0x000000ff
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%tmp3 = and i32 %byte3, 4278190080 ; 0xff000000
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%tmp2 = and i32 %byte2, 16711680 ; 0x00ff0000
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%or0 = or i32 %tmp0, %tmp1
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%or1 = or i32 %tmp2, %tmp3
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%result = or i32 %or0, %or1
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ret i32 %result
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}
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; Invalid pattern involving a unary op
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define i32 @test3(float %x) nounwind {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subl $8, %esp
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; CHECK-NEXT: flds {{[0-9]+}}(%esp)
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; CHECK-NEXT: fnstcw (%esp)
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; CHECK-NEXT: movzwl (%esp), %eax
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; CHECK-NEXT: orl $3072, %eax # imm = 0xC00
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; CHECK-NEXT: movw %ax, {{[0-9]+}}(%esp)
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; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)
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; CHECK-NEXT: fistpl {{[0-9]+}}(%esp)
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; CHECK-NEXT: fldcw (%esp)
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl %ecx, %edx
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; CHECK-NEXT: shll $8, %edx
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: shrl $8, %eax
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; CHECK-NEXT: andl $65280, %ecx # imm = 0xFF00
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; CHECK-NEXT: andl $-16777216, %edx # imm = 0xFF000000
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; CHECK-NEXT: andl $16711680, %eax # imm = 0xFF0000
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; CHECK-NEXT: orl %edx, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: addl $8, %esp
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; CHECK-NEXT: retl
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;
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; CHECK64-LABEL: test3:
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; CHECK64: # %bb.0:
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; CHECK64-NEXT: cvttss2si %xmm0, %ecx
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; CHECK64-NEXT: movl %ecx, %edx
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; CHECK64-NEXT: shll $8, %edx
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; CHECK64-NEXT: movl %ecx, %eax
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; CHECK64-NEXT: shrl $8, %eax
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; CHECK64-NEXT: andl $65280, %ecx # imm = 0xFF00
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; CHECK64-NEXT: andl $-16777216, %edx # imm = 0xFF000000
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; CHECK64-NEXT: andl $16711680, %eax # imm = 0xFF0000
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; CHECK64-NEXT: orl %edx, %eax
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; CHECK64-NEXT: orl %ecx, %eax
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; CHECK64-NEXT: retq
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%integer = fptosi float %x to i32
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%byte0 = shl i32 %integer, 8
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%byte3 = shl i32 %integer, 8
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%byte2 = lshr i32 %integer, 8
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%tmp1 = and i32 %integer, 65280 ; 0x0000ff00
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%tmp0 = and i32 %byte0, 255 ; 0x000000ff
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%tmp3 = and i32 %byte3, 4278190080 ; 0xff000000
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%tmp2 = and i32 %byte2, 16711680 ; 0x00ff0000
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%or0 = or i32 %tmp0, %tmp1
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%or1 = or i32 %tmp2, %tmp3
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%result = or i32 %or0, %or1
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ret i32 %result
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}
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