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clang-p2996/llvm/test/CodeGen/X86/bug47278.mir
Simon Pilgrim d391e4fe84 [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth.

Helps prevent future scheduler model mismatches like those that were only addressed in D44687.

Differential Revision: https://reviews.llvm.org/D113302
2021-11-07 15:06:54 +00:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=i386-unknown-linux-musl -verify-machineinstrs -run-pass=regallocfast -o - %s | FileCheck %s
# Make sure this case doesn't assert or try to assign $ecx to %1 on
# SHRD32rrCL
---
name: foo
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: foo
; CHECK: renamable $eax = IMPLICIT_DEF
; CHECK: renamable $edx = MOVZX32rm8 renamable $eax, 1, $noreg, 0, $noreg :: (load (s8) from `i168* undef` + 20, align 4, basealign 16)
; CHECK: dead renamable $ecx = MOV32rm renamable $eax, 1, $noreg, 0, $noreg :: (load (s32) from `i168* undef` + 12, basealign 16)
; CHECK: renamable $al = MOV8rm killed renamable $eax, 1, $noreg, 0, $noreg :: (load (s8) from `i32* undef`, align 4)
; CHECK: dead renamable $ecx = COPY renamable $edx
; CHECK: dead renamable $ecx = COPY renamable $edx
; CHECK: dead renamable $ecx = COPY renamable $edx
; CHECK: renamable $esi = IMPLICIT_DEF
; CHECK: renamable $ecx = IMPLICIT_DEF
; CHECK: renamable $ecx = CMOV32rr renamable $ecx, killed renamable $esi, 2, implicit undef $eflags
; CHECK: renamable $cl = MOV8ri -128
; CHECK: $cl = IMPLICIT_DEF
; CHECK: renamable $eax = COPY renamable $edx
; CHECK: dead renamable $eax = SHRD32rrCL renamable $eax, killed renamable $edx, implicit-def dead $eflags, implicit killed $cl
; CHECK: RET32
%0:gr32 = IMPLICIT_DEF
%1:gr32 = MOVZX32rm8 %0, 1, $noreg, 0, $noreg :: (load (s8) from `i168* undef` + 20, align 4, basealign 16)
%2:gr32 = MOV32rm %0, 1, $noreg, 0, $noreg :: (load (s32) from `i168* undef` + 12, basealign 16)
%3:gr8 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load (s8) from `i32* undef`, align 4)
%4:gr32 = COPY %1
%5:gr32 = COPY %1
%6:gr32 = COPY %1
%7:gr32 = IMPLICIT_DEF
%8:gr32 = IMPLICIT_DEF
%8:gr32 = CMOV32rr %8, killed %7, 2, implicit undef $eflags
%9:gr8 = MOV8ri -128
%9:gr8 = COPY %3
$cl = IMPLICIT_DEF
%8:gr32 = COPY %1
%8:gr32 = SHRD32rrCL %8, %1, implicit-def dead $eflags, implicit $cl
RET32
...