d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
43 lines
1.4 KiB
YAML
43 lines
1.4 KiB
YAML
# RUN: llc -mtriple=x86_64-apple-darwin -stop-after branch-folder -start-after branch-folder -o - %s | FileCheck %s
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# This test verifies that the machine verifier won't report an error when
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# verifying the PATCHPOINT instruction.
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--- |
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define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 5, i8* null, i32 2, i64 %p1, i64 %p2)
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ret void
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}
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declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
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...
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---
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name: small_patchpoint_codegen
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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- { reg: '$rsi' }
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frameInfo:
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hasPatchPoint: true
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stackSize: 8
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adjustsStack: true
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hasCalls: true
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fixedStack:
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- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
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body: |
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bb.0.entry:
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liveins: $rdi, $rsi, $rbp
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frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
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CFI_INSTRUCTION def_cfa_offset 16
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CFI_INSTRUCTION offset $rbp, -16
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$rbp = frame-setup MOV64rr $rsp
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CFI_INSTRUCTION def_cfa_register $rbp
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; CHECK: PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, implicit-def dead early-clobber $r11, implicit-def $rsp, implicit-def dead $rax
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PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, implicit-def dead early-clobber $r11, implicit-def $rsp, implicit-def dead $rax
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$rbp = POP64r implicit-def $rsp, implicit $rsp
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RET64
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...
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