3969425081
1. Deine FeatureRelax to enable/disable linker relaxation. 2. Define shouldForceRelocation to preserve relocation types even if the fixup can be resolved when linker relaxation enabled. This is necessary for correctness as offsets may change during relaxation. Differential Revision: https://reviews.llvm.org/D46674 llvm-svn: 332318
335 lines
12 KiB
C++
335 lines
12 KiB
C++
//===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVFixupKinds.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class RISCVAsmBackend : public MCAsmBackend {
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const MCSubtargetInfo &STI;
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uint8_t OSABI;
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bool Is64Bit;
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public:
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RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit)
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: MCAsmBackend(), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit) {}
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~RISCVAsmBackend() override {}
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void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target, MutableArrayRef<char> Data,
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uint64_t Value, bool IsResolved) const override;
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std::unique_ptr<MCObjectWriter>
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createObjectWriter(raw_pwrite_stream &OS) const override;
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// If linker relaxation is enabled, always emit relocations even if the fixup
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// can be resolved. This is necessary for correctness as offsets may change
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// during relaxation.
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bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target) override {
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return STI.getFeatureBits()[RISCV::FeatureRelax];
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}
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bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override;
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unsigned getNumFixupKinds() const override {
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return RISCV::NumTargetFixupKinds;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
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const static MCFixupKindInfo Infos[RISCV::NumTargetFixupKinds] = {
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// This table *must* be in the order that the fixup_* kinds are defined in
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// RISCVFixupKinds.h.
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//
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// name offset bits flags
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{ "fixup_riscv_hi20", 12, 20, 0 },
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{ "fixup_riscv_lo12_i", 20, 12, 0 },
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{ "fixup_riscv_lo12_s", 0, 32, 0 },
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{ "fixup_riscv_pcrel_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_riscv_pcrel_lo12_i", 20, 12, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_riscv_pcrel_lo12_s", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel }
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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bool mayNeedRelaxation(const MCInst &Inst) const override;
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unsigned getRelaxedOpcode(unsigned Op) const;
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void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
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MCInst &Res) const override;
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
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};
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bool RISCVAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const {
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int64_t Offset = int64_t(Value);
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switch ((unsigned)Fixup.getKind()) {
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default:
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return false;
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case RISCV::fixup_riscv_rvc_branch:
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// For compressed branch instructions the immediate must be
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// in the range [-256, 254].
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return Offset > 254 || Offset < -256;
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case RISCV::fixup_riscv_rvc_jump:
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// For compressed jump instructions the immediate must be
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// in the range [-2048, 2046].
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return Offset > 2046 || Offset < -2048;
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}
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}
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void RISCVAsmBackend::relaxInstruction(const MCInst &Inst,
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const MCSubtargetInfo &STI,
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MCInst &Res) const {
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// TODO: replace this with call to auto generated uncompressinstr() function.
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switch (Inst.getOpcode()) {
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default:
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llvm_unreachable("Opcode not expected!");
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case RISCV::C_BEQZ:
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// c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
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Res.setOpcode(RISCV::BEQ);
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Res.addOperand(Inst.getOperand(0));
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Res.addOperand(MCOperand::createReg(RISCV::X0));
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Res.addOperand(Inst.getOperand(1));
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break;
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case RISCV::C_BNEZ:
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// c.bnez $rs1, $imm -> bne $rs1, X0, $imm.
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Res.setOpcode(RISCV::BNE);
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Res.addOperand(Inst.getOperand(0));
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Res.addOperand(MCOperand::createReg(RISCV::X0));
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Res.addOperand(Inst.getOperand(1));
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break;
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case RISCV::C_J:
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// c.j $imm -> jal X0, $imm.
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Res.setOpcode(RISCV::JAL);
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Res.addOperand(MCOperand::createReg(RISCV::X0));
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Res.addOperand(Inst.getOperand(0));
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break;
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case RISCV::C_JAL:
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// c.jal $imm -> jal X1, $imm.
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Res.setOpcode(RISCV::JAL);
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Res.addOperand(MCOperand::createReg(RISCV::X1));
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Res.addOperand(Inst.getOperand(0));
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break;
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}
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}
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// Given a compressed control flow instruction this function returns
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// the expanded instruction.
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unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
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switch (Op) {
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default:
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return Op;
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case RISCV::C_BEQZ:
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return RISCV::BEQ;
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case RISCV::C_BNEZ:
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return RISCV::BNE;
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case RISCV::C_J:
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case RISCV::C_JAL: // fall through.
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return RISCV::JAL;
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}
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}
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bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
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return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
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}
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bool RISCVAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
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unsigned MinNopLen = HasStdExtC ? 2 : 4;
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if ((Count % MinNopLen) != 0)
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return false;
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// The canonical nop on RISC-V is addi x0, x0, 0.
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uint64_t Nop32Count = Count / 4;
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for (uint64_t i = Nop32Count; i != 0; --i)
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OW->write32(0x13);
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// The canonical nop on RVC is c.nop.
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if (HasStdExtC) {
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uint64_t Nop16Count = (Count - Nop32Count * 4) / 2;
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for (uint64_t i = Nop16Count; i != 0; --i)
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OW->write16(0x01);
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}
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return true;
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}
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static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
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MCContext &Ctx) {
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unsigned Kind = Fixup.getKind();
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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return Value;
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case RISCV::fixup_riscv_lo12_i:
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case RISCV::fixup_riscv_pcrel_lo12_i:
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return Value & 0xfff;
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case RISCV::fixup_riscv_lo12_s:
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case RISCV::fixup_riscv_pcrel_lo12_s:
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return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
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case RISCV::fixup_riscv_hi20:
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case RISCV::fixup_riscv_pcrel_hi20:
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// Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
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return ((Value + 0x800) >> 12) & 0xfffff;
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case RISCV::fixup_riscv_jal: {
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if (!isInt<21>(Value))
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Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
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if (Value & 0x1)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
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// Need to produce imm[19|10:1|11|19:12] from the 21-bit Value.
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unsigned Sbit = (Value >> 20) & 0x1;
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unsigned Hi8 = (Value >> 12) & 0xff;
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unsigned Mid1 = (Value >> 11) & 0x1;
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unsigned Lo10 = (Value >> 1) & 0x3ff;
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// Inst{31} = Sbit;
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// Inst{30-21} = Lo10;
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// Inst{20} = Mid1;
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// Inst{19-12} = Hi8;
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Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;
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return Value;
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}
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case RISCV::fixup_riscv_branch: {
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if (!isInt<13>(Value))
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Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
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if (Value & 0x1)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
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// Need to extract imm[12], imm[10:5], imm[4:1], imm[11] from the 13-bit
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// Value.
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unsigned Sbit = (Value >> 12) & 0x1;
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unsigned Hi1 = (Value >> 11) & 0x1;
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unsigned Mid6 = (Value >> 5) & 0x3f;
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unsigned Lo4 = (Value >> 1) & 0xf;
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// Inst{31} = Sbit;
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// Inst{30-25} = Mid6;
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// Inst{11-8} = Lo4;
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// Inst{7} = Hi1;
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Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
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return Value;
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}
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case RISCV::fixup_riscv_rvc_jump: {
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// Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
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unsigned Bit11 = (Value >> 11) & 0x1;
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unsigned Bit4 = (Value >> 4) & 0x1;
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unsigned Bit9_8 = (Value >> 8) & 0x3;
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unsigned Bit10 = (Value >> 10) & 0x1;
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unsigned Bit6 = (Value >> 6) & 0x1;
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unsigned Bit7 = (Value >> 7) & 0x1;
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unsigned Bit3_1 = (Value >> 1) & 0x7;
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unsigned Bit5 = (Value >> 5) & 0x1;
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Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
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(Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
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return Value;
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}
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case RISCV::fixup_riscv_rvc_branch: {
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// Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5]
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unsigned Bit8 = (Value >> 8) & 0x1;
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unsigned Bit7_6 = (Value >> 6) & 0x3;
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unsigned Bit5 = (Value >> 5) & 0x1;
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unsigned Bit4_3 = (Value >> 3) & 0x3;
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unsigned Bit2_1 = (Value >> 1) & 0x3;
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Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |
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(Bit5 << 2);
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return Value;
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}
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}
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}
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static unsigned getSize(unsigned Kind) {
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switch (Kind) {
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default:
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return 4;
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case RISCV::fixup_riscv_rvc_jump:
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case RISCV::fixup_riscv_rvc_branch:
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return 2;
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}
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}
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void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target,
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MutableArrayRef<char> Data, uint64_t Value,
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bool IsResolved) const {
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MCContext &Ctx = Asm.getContext();
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MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
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if (!Value)
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return; // Doesn't change encoding.
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// Apply any target-specific value adjustments.
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Value = adjustFixupValue(Fixup, Value, Ctx);
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// Shift the value into position.
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Value <<= Info.TargetOffset;
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unsigned Offset = Fixup.getOffset();
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unsigned FullSize = getSize(Fixup.getKind());
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#ifndef NDEBUG
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unsigned NumBytes = (Info.TargetSize + 7) / 8;
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assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
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#endif
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// For each byte of the fragment that the fixup touches, mask in the
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// bits from the fixup value.
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for (unsigned i = 0; i != FullSize; ++i) {
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Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
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}
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}
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std::unique_ptr<MCObjectWriter>
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RISCVAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
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return createRISCVELFObjectWriter(OS, OSABI, Is64Bit);
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}
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} // end anonymous namespace
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MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options) {
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const Triple &TT = STI.getTargetTriple();
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uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
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return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit());
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}
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