Files
clang-p2996/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Alex Bradbury fda6037e98 [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot
This causes some slight shuffling but no meaningful codegen differences on the 
corpus I used for testing, but it has a larger impact when combined with e.g. 
rematerialisation. Regardless, it makes sense to report as accurate 
target-specific information as possible.

llvm-svn: 330949
2018-04-26 15:34:27 +00:00

14 KiB