1103a2a337
Kernel descriptor attributes, with their respective emit and asm parse functionality, converted to MCExpr. Relands #80855 with fixes
99 lines
4.1 KiB
C++
99 lines
4.1 KiB
C++
//===--- AMDHSAKernelDescriptor.h -----------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUMCKernelDescriptor.h"
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#include "AMDGPUMCTargetDesc.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/TargetParser/TargetParser.h"
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using namespace llvm;
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using namespace llvm::AMDGPU;
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MCKernelDescriptor
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MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI,
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MCContext &Ctx) {
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IsaVersion Version = getIsaVersion(STI->getCPU());
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MCKernelDescriptor KD;
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const MCExpr *ZeroMCExpr = MCConstantExpr::create(0, Ctx);
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const MCExpr *OneMCExpr = MCConstantExpr::create(1, Ctx);
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KD.group_segment_fixed_size = ZeroMCExpr;
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KD.private_segment_fixed_size = ZeroMCExpr;
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KD.compute_pgm_rsrc1 = ZeroMCExpr;
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KD.compute_pgm_rsrc2 = ZeroMCExpr;
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KD.compute_pgm_rsrc3 = ZeroMCExpr;
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KD.kernarg_size = ZeroMCExpr;
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KD.kernel_code_properties = ZeroMCExpr;
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KD.kernarg_preload = ZeroMCExpr;
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MCKernelDescriptor::bits_set(
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KD.compute_pgm_rsrc1,
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MCConstantExpr::create(amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE, Ctx),
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amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64_SHIFT,
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amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Ctx);
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if (Version.Major < 12) {
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MCKernelDescriptor::bits_set(
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KD.compute_pgm_rsrc1, OneMCExpr,
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amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP_SHIFT,
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amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP, Ctx);
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MCKernelDescriptor::bits_set(
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KD.compute_pgm_rsrc1, OneMCExpr,
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amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE_SHIFT,
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amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE, Ctx);
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}
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MCKernelDescriptor::bits_set(
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KD.compute_pgm_rsrc2, OneMCExpr,
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amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT,
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amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Ctx);
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if (Version.Major >= 10) {
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if (STI->getFeatureBits().test(FeatureWavefrontSize32))
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MCKernelDescriptor::bits_set(
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KD.kernel_code_properties, OneMCExpr,
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amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT,
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amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, Ctx);
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if (!STI->getFeatureBits().test(FeatureCuMode))
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MCKernelDescriptor::bits_set(
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KD.compute_pgm_rsrc1, OneMCExpr,
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amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE_SHIFT,
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amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE, Ctx);
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MCKernelDescriptor::bits_set(
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KD.compute_pgm_rsrc1, OneMCExpr,
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amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED_SHIFT,
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amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED, Ctx);
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}
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if (AMDGPU::isGFX90A(*STI) && STI->getFeatureBits().test(FeatureTgSplit))
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MCKernelDescriptor::bits_set(
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KD.compute_pgm_rsrc3, OneMCExpr,
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amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
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amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, Ctx);
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return KD;
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}
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void MCKernelDescriptor::bits_set(const MCExpr *&Dst, const MCExpr *Value,
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uint32_t Shift, uint32_t Mask,
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MCContext &Ctx) {
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auto Sft = MCConstantExpr::create(Shift, Ctx);
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auto Msk = MCConstantExpr::create(Mask, Ctx);
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Dst = MCBinaryExpr::createAnd(Dst, MCUnaryExpr::createNot(Msk, Ctx), Ctx);
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Dst = MCBinaryExpr::createOr(Dst, MCBinaryExpr::createShl(Value, Sft, Ctx),
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Ctx);
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}
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const MCExpr *MCKernelDescriptor::bits_get(const MCExpr *Src, uint32_t Shift,
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uint32_t Mask, MCContext &Ctx) {
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auto Sft = MCConstantExpr::create(Shift, Ctx);
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auto Msk = MCConstantExpr::create(Mask, Ctx);
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return MCBinaryExpr::createLShr(MCBinaryExpr::createAnd(Src, Msk, Ctx), Sft,
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Ctx);
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}
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