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clang-p2996/llvm/test/CodeGen/RISCV
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Craig Topper 644899addd [RISCV][GISel] Port portions of float-intrinsics.ll and double-intrinsics.ll. NFC 
Remove the legalizer test for the same intrinsics as it is no longer
interesting with end to end tests.
2024-09-18 13:13:34 -07:00
..
GlobalISel
[RISCV][GISel] Port portions of float-intrinsics.ll and double-intrinsics.ll. NFC
2024-09-18 13:13:34 -07:00
intrinsics
…
rvv
[RISCV] Remove unnecessary vand.vi from vXi1 and nvXvi1 VECTOR_REVERSE codegen. (#109071)
2024-09-18 09:43:48 -07:00
abds-neg.ll
[DAG] Fix typo in i64/i128 abdu/abds tests
2024-09-04 11:59:10 +01:00
abds.ll
[DAG] Add test coverage for ABD "sub of selects" patterns based off #53045
2024-09-11 15:18:29 +01:00
abdu-neg.ll
[DAG] Fix typo in i64/i128 abdu/abds tests
2024-09-04 11:59:10 +01:00
abdu.ll
[DAG] Add test coverage for ABD "sub of selects" patterns based off #53045
2024-09-11 15:18:29 +01:00
add-before-shl.ll
…
add-imm.ll
…
addc-adde-sube-subc.ll
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addcarry.ll
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addimm-mulimm.ll
[RISCV] Use RISCVISD::SHL_ADD in transformAddShlImm (#89832)
2024-05-13 09:48:46 -07:00
addrspacecast.ll
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aext-to-sext.ll
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aext.ll
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align-loops.ll
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align.ll
…
alloca.ll
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allow-check.ll
[CodeGen] Add default lowering for llvm.allow.{runtime,ubsan}.check() (#86049)
2024-03-31 22:19:33 -07:00
alu8.ll
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alu16.ll
…
alu32.ll
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alu64.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
analyze-branch.ll
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and-add-lsr.ll
[DAG] Avoid a crash when checking size of scalable type in visitANDLike
2024-02-05 14:30:10 -08:00
and.ll
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arith-with-overflow.ll
…
atomic-cmpxchg-branch-on-result.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
atomic-fence.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
atomic-load-store.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
atomic-rmw-discard.ll
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atomic-rmw-sub.ll
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atomic-rmw.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
atomic-signext.ll
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
2024-07-23 08:06:15 +01:00
atomicrmw-cond-sub-clamp.ll
Add usub_cond and usub_sat operations to atomicrmw (#105568)
2024-09-06 16:19:20 +01:00
atomicrmw-uinc-udec-wrap.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
attributes-module-flag.ll
[RISCV] Make M imply Zmmul (#95070)
2024-06-21 11:11:10 +08:00
attributes.ll
[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)
2024-08-21 19:23:07 -07:00
avgceils.ll
[RISCV] Add scalar type test coverage for ISD::AVG nodes
2024-06-15 16:15:50 +01:00
avgceilu.ll
[RISCV] Add scalar type test coverage for ISD::AVG nodes
2024-06-15 16:15:50 +01:00
avgfloors.ll
[RISCV] Add scalar type test coverage for ISD::AVG nodes
2024-06-15 16:15:50 +01:00
avgflooru.ll
Recommit "[DAG] Reducing instructions by better legalization handling of AVGFLOORU for illegal data types" (#101223)
2024-07-30 19:00:46 -07:00
bf16-promote.ll
…
bfloat-arith.ll
[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)
2024-09-02 22:04:09 -07:00
bfloat-br-fcmp.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-convert.ll
[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (#107011)
2024-09-03 15:34:25 -07:00
bfloat-fcmp.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-frem.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-imm.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-isnan.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-mem.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-select-fcmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
bfloat-select-icmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
bfloat.ll
…
bitextract-mac.ll
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bitreverse-shift.ll
[DAG] Fold bitreverse(shl/srl(bitreverse(x),y)) -> srl/shl(x,y) (#89897)
2024-05-06 11:13:05 +01:00
bittest.ll
…
blockaddress.ll
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branch_zero.ll
…
branch-on-zero.ll
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branch-opt.ll
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branch-opt.mir
[RISCV] Make sure ADDI replacement in optimizeCondBranch has a virtual reg destination. (#81938)
2024-02-15 16:34:40 -08:00
branch-relaxation.ll
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branch.ll
…
bswap-bitreverse.ll
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bswap-shift.ll
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byval.ll
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callee-saved-fpr32s.ll
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callee-saved-fpr64s.ll
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callee-saved-gprs.ll
[RISCV] Lower the TransientStackAlignment to the ABI alignment for rv32e/rv64e.
2024-02-09 21:48:11 -08:00
calling-conv-half.ll
[RISCV] Add constant folding combine for FMV_X_ANYEXTW/H. (#106653)
2024-08-30 09:43:42 -07:00
calling-conv-ilp32-ilp32f-common.ll
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
…
calling-conv-ilp32.ll
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calling-conv-ilp32d.ll
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calling-conv-ilp32e.ll
[RISCV] Register fixed stack slots for callee saved registers for -msave-restore/Zcmp (#81392)
2024-02-13 14:59:28 -08:00
calling-conv-ilp32f-ilp32d-common.ll
…
calling-conv-lp64-lp64f-common.ll
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calling-conv-lp64-lp64f-lp64d-common.ll
[mi-sched] Suppress register pressure with i64. (#88256)
2024-04-15 13:11:45 +08:00
calling-conv-lp64.ll
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calling-conv-lp64e.ll
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calling-conv-rv32f-ilp32.ll
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calling-conv-rv32f-ilp32e.ll
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calling-conv-sext-zext.ll
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calling-conv-vector-float.ll
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calling-conv-vector-on-stack.ll
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calls.ll
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
clear-cache.ll
[RISCV] Lower llvm.clear_cache to __riscv_flush_icache for glibc targets (#93481)
2024-06-20 07:27:07 +02:00
cm_mvas_mvsa.ll
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cm_mvas_mvsa.mir
[RISCV] Add scheduling info for Zcmp (#82719)
2024-02-23 15:44:57 -08:00
cmov-branch-opt.ll
[RISCV] Graduate Zicond to non-experimental (#79811)
2024-01-29 15:58:54 +00:00
cmp-bool.ll
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codemodel-lowering.ll
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
compress-double.ll
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compress-float.ll
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compress-inline-asm.ll
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compress-opt-branch.ll
[RISCV] Add Zca predicate to BrccCompressOpt patterns used for MinSize.
2024-04-05 12:39:39 -07:00
compress-opt-select.ll
[RISCV] Autogenerate compress-opt-select.ll
2024-09-17 08:47:20 -07:00
compress.ll
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condbinops.ll
[RISCV] Graduate Zicond to non-experimental (#79811)
2024-01-29 15:58:54 +00:00
condops.ll
[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)
2024-07-27 17:26:32 -07:00
convert-highly-predictable-select-to-branch.ll
[RISCV] Add FeaturePredictableSelectIsExpensive
2024-07-05 11:29:42 +08:00
copy-frameindex.mir
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
copyprop.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
copysign-casts.ll
[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)
2024-09-02 22:04:09 -07:00
ctlz-cttz-ctpop.ll
[RISCV] Simplify (srl (and X, Mask), Const) to TH_EXTU (#102802)
2024-08-16 14:23:00 +08:00
ctz_zero_return_test.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
disable-tail-calls.ll
…
disjoint.ll
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div_minsize.ll
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div-by-constant.ll
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div-pow2.ll
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div.ll
[TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (#101751)
2024-08-14 08:44:57 -07:00
double_reduct.ll
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double-arith-strict.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-arith.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
double-bitmanip-dagcombines.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
double-br-fcmp.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-calling-conv.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-convert-strict.ll
[RISCV] Add some Zfinx instructions to hasAllNBitUsers.
2024-08-08 17:33:54 -07:00
double-convert.ll
[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)
2024-09-05 08:42:13 -07:00
double-fcmp-strict.ll
[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)
2024-09-12 18:40:52 -07:00
double-fcmp.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-frem.ll
…
double-imm.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
double-intrinsics-strict.ll
[clang] Reland Add tanf16 builtin and support for tan constrained intrinsic (#94559)
2024-06-10 20:46:26 -04:00
double-intrinsics.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
double-isnan.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-maximum-minimum.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-mem.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-previous-failure.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-round-conv-sat.ll
[DAGCombiner] Push freeze through SETCC and SELECT_CC (#64718)
2024-07-22 16:01:59 +02:00
double-round-conv.ll
[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)
2024-09-05 08:42:13 -07:00
double-select-fcmp.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-select-icmp.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-stack-spill-restore.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-zfa.ll
[RISCV] Expand Zfa fli+fneg cases during lowering instead of during isel. (#108316)
2024-09-11 22:31:45 -07:00
dso_local_equivalent.ll
…
dwarf-eh.ll
…
early-clobber-tied-def-subreg-liveness.ll
[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)
2024-08-31 19:28:36 +08:00
eh-dwarf-cfa.ll
…
elf-preemption.ll
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emutls.ll
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exception-pointer-register.ll
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fastcc-bf16.ll
[RISCV] Add fastcc support for bf16 with Zfbfmin.
2024-09-06 16:50:25 -07:00
fastcc-float.ll
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fastcc-half.ll
[RISCV] Add Zfhmin fastcc test. NFC
2024-09-06 16:50:24 -07:00
fastcc-int.ll
[RISCV] Remove x7 from fastcc list. (#96729)
2024-07-17 08:37:55 +08:00
fastcc-without-f-reg.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
fixups-diff.ll
[MC] Rename temporary symbols of empty name to ".L0 " (#89693)
2024-04-26 08:30:27 -07:00
fli-licm.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
float-arith-strict.ll
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float-arith.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
float-bit-preserving-dagcombines.ll
…
float-bitmanip-dagcombines.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
float-br-fcmp.ll
…
float-convert-strict.ll
[RISCV] Add some Zfinx instructions to hasAllNBitUsers.
2024-08-08 17:33:54 -07:00
float-convert.ll
[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)
2024-09-05 08:42:13 -07:00
float-fcmp-strict.ll
[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)
2024-09-12 18:40:52 -07:00
float-fcmp.ll
…
float-frem.ll
…
float-imm.ll
[RISCV] Add constant folding combine for FMV_X_ANYEXTW/H. (#106653)
2024-08-30 09:43:42 -07:00
float-intrinsics-strict.ll
[RISCV] Correct the rounding mode for llvm.lround.i64.f32 with RV64+Zfinx.
2024-09-01 13:26:38 -07:00
float-intrinsics.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
float-isnan.ll
…
float-maximum-minimum.ll
…
float-mem.ll
…
float-round-conv-sat.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
float-round-conv.ll
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float-select-fcmp.ll
…
float-select-icmp.ll
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float-select-verify.ll
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
float-zfa.ll
[RISCV] Expand Zfa fli+fneg cases during lowering instead of during isel. (#108316)
2024-09-11 22:31:45 -07:00
flt-rounds.ll
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fmax-fmin.ll
…
fold-addi-loadstore.ll
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
fold-binop-into-select-return-constant.ll
[RISCV] Add a check in lowerSELECT after foldBinOpIntoSelectIfProfitable (#97391)
2024-07-05 10:55:36 +08:00
fold-binop-into-select.ll
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forced-atomics.ll
Reapply "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" (#90267)
2024-07-08 13:35:36 -07:00
fp16-promote.ll
…
fp128.ll
…
fpclamptosat.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
fpenv.ll
…
frame-info.ll
…
frame.ll
…
frameaddr-returnaddr.ll
…
frm-dependency.ll
…
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
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ghccc-nest.ll
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ghccc-rv32.ll
…
ghccc-rv64.ll
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ghccc-without-f-reg.ll
…
global-merge-minsize-smalldata-nonzero.ll
[GlobalMerge] Add MinSize feature to the GlobalMerge Pass. (#93686)
2024-06-03 09:10:56 -04:00
global-merge-minsize-smalldata-zero.ll
[GlobalMerge] Add MinSize feature to the GlobalMerge Pass. (#93686)
2024-06-03 09:10:56 -04:00
global-merge-minsize.ll
[GlobalMerge] Add MinSize feature to the GlobalMerge Pass. (#93686)
2024-06-03 09:10:56 -04:00
global-merge-offset.ll
…
global-merge.ll
…
graalcc.ll
…
half-arith-strict.ll
[RISCV] Custom legalize f16/bf16 FNEG/FABS with Zfhmin/Zbfmin. (#106886)
2024-08-31 23:57:40 -07:00
half-arith.ll
[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)
2024-09-05 08:42:13 -07:00
half-bitmanip-dagcombines.ll
[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)
2024-09-02 22:04:09 -07:00
half-br-fcmp.ll
…
half-convert-strict.ll
[RISCV] Support STRICT_UINT_TO_FP and STRICT_SINT_TO_FP (#102503)
2024-09-17 11:21:52 -03:00
half-convert.ll
[LegalizeIntegerTypes] Simplify ExpandIntRes_FP_TO_XINT when operand needs to be SoftPromoted. (#107634)
2024-09-12 08:28:06 -07:00
half-fcmp-strict.ll
[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)
2024-09-12 18:40:52 -07:00
half-fcmp.ll
…
half-frem.ll
…
half-imm.ll
[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)
2024-09-05 08:42:13 -07:00
half-intrinsics.ll
[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)
2024-09-05 08:42:13 -07:00
half-isnan.ll
…
half-maximum-minimum.ll
…
half-mem.ll
…
half-round-conv-sat.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
half-round-conv.ll
[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)
2024-09-05 08:42:13 -07:00
half-select-fcmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
half-select-icmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
half-zfa-fli.ll
…
half-zfa.ll
[RISCV] Expand Zfa fli+fneg cases during lowering instead of during isel. (#108316)
2024-09-11 22:31:45 -07:00
hoist-global-addr-base.ll
…
hwasan-check-memaccess.ll
…
i32-icmp.ll
…
i64-icmp.ll
…
iabs.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
idiv_large.ll
…
imm-cse.ll
…
imm.ll
[RISCV] Improve hasAllNBitUsers for users of SLLI.
2024-08-03 18:19:40 -07:00
indirectbr.ll
…
init-array.ll
…
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
[RISCV] Use BuildPairF64 and SplitF64 for bitcast i64<->f64 on rv32 regardless of Zfa. (#85982)
2024-03-21 08:52:51 -07:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
…
inline-asm-mem-constraint-2.ll
[test][RISCV] Precommit inline asm tests for #104925
2024-08-26 13:30:23 +03:00
inline-asm-mem-constraint.ll
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
inline-asm-s-constraint-error.ll
[RISCV] Support constraint "s" (#80201)
2024-02-01 10:18:42 -08:00
inline-asm-s-constraint.ll
[RISCV] Support constraint "s" (#80201)
2024-02-01 10:18:42 -08:00
inline-asm-zfh-constraint-f.ll
…
inline-asm.ll
…
inline-option-directive.ll
…
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
[RISCV] Remove interrupt handler special case from RISCVFrameLowering::determineCalleeSaves. (#88069)
2024-04-10 10:28:54 -07:00
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
[RISCV] Remove interrupt handler special case from RISCVFrameLowering::determineCalleeSaves. (#88069)
2024-04-10 10:28:54 -07:00
intrinsic-cttz-elts-vscale.ll
[RISCV] Support postRA vsetvl insertion pass (#70549)
2024-05-21 14:42:55 +08:00
intrinsic-cttz-elts.ll
[RISCV] Provide a more efficient lowering for experimental.cttz.elts. (#88552)
2024-04-15 18:38:54 -07:00
isel-optnone.ll
…
jumptable-swguarded.ll
[RISCV] Insert simple landing pad for taken address labels. (#91855)
2024-08-06 22:04:48 +08:00
jumptable.ll
…
kcfi-isel-mir.ll
…
kcfi-mir.ll
…
kcfi-patchable-function-prefix.ll
…
kcfi.ll
…
lack-of-signed-truncation-check.ll
[RISCV] Select (and (sra x, c2), c1) as (srli (srai x, c2-c3), c3). (#101868)
2024-08-04 22:35:38 -07:00
large-stack.ll
…
legalize-fneg.ll
…
libcall-tail-calls.ll
…
lit.local.cfg
…
live-sp.mir
[MachineFrameInfo] Refactoring around computeMaxcallFrameSize() (NFC) (#78001)
2024-03-18 10:37:59 -04:00
llvm.exp10.ll
…
llvm.frexp.ll
…
load-setcc-combine.ll
[DAGCombiner] Allow tryToFoldExtOfLoad to use a sextload for zext nneg. (#81714)
2024-02-17 11:37:13 -08:00
local-stack-slot-allocation.ll
[RISCV] Don't exlude the frame pointer from the callee saved registers in RISCVRegisterInfo::needsFrameBaseReg.
2024-05-13 12:58:30 -07:00
loop-strength-reduce-add-cheaper-than-mul.ll
…
loop-strength-reduce-loop-invar.ll
[RISCV][LSR] Account for temporary register for base addition (#92296)
2024-05-22 13:38:39 -07:00
lpad.ll
[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)
2024-08-08 13:22:59 +08:00
lsr-legaladdimm.ll
…
machine-combiner-mir.ll
…
machine-combiner-strategies.ll
…
machine-combiner.ll
[RISCV] Model integer min max instructions from Zbb execute in late-B ALU
2024-03-14 06:02:53 -07:00
machine-combiner.mir
…
machine-cp.mir
…
machine-cse.ll
…
machine-outliner-and-machine-copy-propagation.ll
…
machine-outliner-cfi.mir
…
machine-outliner-patchable.ll
…
machine-outliner-position.mir
…
machine-outliner-throw.ll
…
machine-sink-load-immediate.ll
[RISCV] Add a testcase for an unprofitable machine-sink issue
2024-09-16 14:17:42 -07:00
machinelicm-address-pseudos.ll
…
machinelicm-constant-phys-reg.ll
[MachineLICM] Hoist copies of constant physical register (#93285)
2024-05-29 14:10:01 +08:00
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
[RISCV] Don't outline pcrel_lo when the function has a section prefix (#107943)
2024-09-11 09:53:11 -07:00
machineoutliner.mir
…
MachineSink-implicit-x0.mir
…
macro-fusion-lui-addi.ll
…
macro-fusions.mir
…
make-compressible-for-store-address.mir
…
make-compressible-rv64.mir
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
make-compressible-zbc.mir
[RISCV] Fix IR for store_large_offset_no_opt_i16 in make-compressible-zbc.mir. NFC
2024-09-16 12:51:07 -07:00
make-compressible.mir
[RISCV] Teach RISCVMakeCompressible handle Zca/Zcf/Zce/Zcd. (#81844)
2024-02-22 15:51:19 +08:00
mem64.ll
…
mem.ll
…
memcpy-inline.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
memcpy.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
memset-inline.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
min-max.ll
…
mir-target-flags.ll
…
misched-load-clustering.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
misched-postra-direction.mir
[CodeGen][MISched] Add misched post-regalloc bidirectional scheduling (#77138)
2024-03-25 10:10:35 -04:00
miss-sp-restore-eh.ll
…
module-elf-flags.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
module-target-abi2.ll
…
module-target-abi3.ll
…
module-target-abi.ll
…
mul.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
musttail-call.ll
…
narrow-shl-cst.ll
…
neg-abs.ll
…
nest-register.ll
…
nomerge.ll
…
nontemporal-scalable.ll
…
nontemporal.ll
…
O0-pipeline.ll
[ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes (#86149)
2024-08-29 17:53:32 +01:00
O3-pipeline.ll
Fix for llvm/test/CodeGen/RISCV/O3-pipeline.ll (#108050)
2024-09-10 09:25:00 -07:00
opt-w-instrs.mir
[RISCV] Rework isSignExtendingOpW to store Register in the worklist.
2024-02-03 23:40:09 -08:00
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax-relocation.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
…
or-is-add.ll
[RISCV] Use disjoint flag in or_is_add.
2024-01-30 22:12:28 -08:00
out-of-reach-emergency-slot.mir
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
overflow-intrinsic-optimizations.ll
…
overflow-intrinsics.ll
…
patchable-function-entry.ll
…
pei-crash.ll
…
pic-models.ll
…
pr40333.ll
…
pr51206.ll
[CGP] Permit tail call optimization on undefined return value
2024-02-22 10:09:15 +01:00
pr53662.mir
…
pr55201.ll
…
pr56110.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
pr56457.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
pr58025.ll
…
pr58286.ll
…
pr58511.ll
…
pr63365.ll
…
pr63816.ll
…
pr64503.ll
…
pr64645.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
pr64772.ll
…
pr64935.ll
…
pr65025.ll
…
pr66603.ll
…
pr68855.ll
…
pr69586.ll
[RISCV] Support postRA vsetvl insertion pass (#70549)
2024-05-21 14:42:55 +08:00
pr80052.mir
[StackSlotColoring] Ignore non-spill objects in RemoveDeadStores. (#80242)
2024-02-01 13:25:15 -08:00
pr84200.ll
[RISCV] Insert a freeze before converting select to AND/OR. (#84232)
2024-03-07 15:03:51 -08:00
pr84653_pr85190.ll
[DAGCombiner] Freeze maybe poison operands when folding select to logic (#84924)
2024-07-22 17:19:46 +02:00
pr88365.ll
[LLVM] [MC] Update frame layout & CFI generation to handle frames larger than 2gb (#99263)
2024-07-23 09:43:30 -07:00
pr90652.ll
[RISCV][ISel] Fix types in tryFoldSelectIntoOp (#90659)
2024-05-01 06:51:36 +08:00
pr90730.ll
[RISCV][ISel] Allow opaque constants in hasAndNotCompare (#92926)
2024-05-22 00:48:26 +08:00
pr92193.ll
[DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on type mismatch (#92195)
2024-05-15 12:39:28 -07:00
pr94145.ll
[DAG] canCreateUndefOrPoison - fix missing argument typo
2024-06-02 10:34:48 +01:00
pr94265.ll
[RISCV] Replace hasStdExtV with hasVInstructions in isTruncateFree.
2024-07-29 17:15:02 -07:00
pr95271.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
pr95284.ll
[DAG] combineShiftToAVG - don't create avgfloor with scalar constant operands unless legal.
2024-06-13 12:37:43 +01:00
pr96366.ll
[SDAG] Intersect poison-generating flags after CSE (#97434)
2024-07-03 20:32:46 +08:00
pr97304.ll
[RISCV] Copy call frame size when splitting basic block in emitSelectPseudo. (#99823)
2024-07-22 09:21:01 -07:00
prefer-w-inst.ll
[RISCV] Generate more W instructons
2024-04-16 15:37:31 +08:00
prefer-w-inst.mir
[RISCV] Generate more W instructons
2024-04-16 15:37:31 +08:00
prefetch.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
prolog-epilogue.ll
[RISCV] Exploit sh3add/sh2add for stack offsets by shifted 12-bit constants (#87950)
2024-04-08 14:53:21 -07:00
push-pop-opt-crash.ll
[RISCV] Fix typo in ABI name in test. NFC
2024-02-09 11:46:23 -08:00
push-pop-popret.ll
[RISCV] Add X27 to SavedRegs when X26 is in SavedRegs for cm.push/pop (#92067)
2024-05-14 08:06:10 -07:00
readcyclecounter.ll
…
readsteadycounter.ll
[RISCV] Support llvm.readsteadycounter intrinsic
2024-02-21 13:12:14 +08:00
reduce-unnecessary-extension.ll
…
reduction-formation.ll
…
redundant-copy-from-tail-duplicate.ll
[RISCV] Add reductions to list of roots in tryToReduceVL (#107595)
2024-09-10 18:47:20 -07:00
regalloc-last-chance-recoloring-failure.ll
[InitUndef] Enable the InitUndef pass on non-AMDGPU targets (#108353)
2024-09-16 09:48:25 +02:00
relax-per-target-feature.ll
…
rem.ll
…
remat.ll
…
renamable-copy.mir
[TII][RISCV] Add renamable bit to copyPhysReg (#91179)
2024-08-27 10:08:43 +08:00
repeated-fp-divisors.ll
…
reserved-reg-errors.ll
…
reserved-regs.ll
…
riscv-codegen-prepare-atp.ll
[RISCV] Implement RISCVTTIImpl::shouldConsiderAddressTypePromotion for RISCV (#102560)
2024-08-15 10:37:04 +08:00
riscv-codegenprepare-asm.ll
…
riscv-codegenprepare.ll
[RISCV] Don't look for sext in RISCVCodeGenPrepare::visitAnd.
2024-01-19 14:44:47 -08:00
riscv-func-target-feature.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
riscv-shifted-extend.ll
…
riscv-tail-dup-size.ll
[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873)
2024-08-01 12:24:25 +08:00
rotl-rotr.ll
…
rv32-fuchsia.ll
…
rv32e.ll
…
rv32i-rv64i-float-double.ll
…
rv32i-rv64i-half.ll
…
rv32xtheadba.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
rv32xtheadbb.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
rv32xtheadbs.ll
…
rv32zba.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
rv32zbb-intrinsic.ll
…
rv32zbb-zbkb.ll
[RISCV] Insert a freeze before converting select to AND/OR. (#84232)
2024-03-07 15:03:51 -08:00
rv32zbb.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbkb-intrinsic.ll
…
rv32zbkb.ll
[RISCV] Support zext.h mnemonic with Zbkb. (#96821)
2024-06-27 09:31:26 -07:00
rv32zbkx-intrinsic.ll
…
rv32zbs.ll
[RISCV] Insert a freeze before converting select to AND/OR. (#84232)
2024-03-07 15:03:51 -08:00
rv32zimop-intrinsic.ll
[RISCV] Zimop/Zcmop are ratified
2024-04-08 16:40:02 +08:00
rv32zknd-intrinsic-autoupgrade.ll
…
rv32zknd-intrinsic.ll
…
rv32zkne-intrinsic-autoupgrade.ll
…
rv32zkne-intrinsic.ll
…
rv32zknh-intrinsic.ll
…
rv32zksed-intrinsic-autoupgrade.ll
…
rv32zksed-intrinsic.ll
…
rv32zksh-intrinsic.ll
…
rv64-large-stack.ll
…
rv64-patchpoint.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-stackmap-frame-setup.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
rv64-stackmap-nops.ll
…
rv64-stackmap.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
rv64-statepoint-call-lowering-x1.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-statepoint-call-lowering-x2.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-statepoint-call-lowering.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-typepromotion.ll
[RISCV][TypePromotion] Dont generate truncs if PromotedType is greater than Source Type (#86941)
2024-03-28 21:22:05 -07:00
rv64d-double-convert-strict.ll
…
rv64d-double-convert.ll
…
rv64e.ll
…
rv64f-float-convert-strict.ll
…
rv64f-float-convert.ll
…
rv64i-complex-float.ll
…
rv64i-demanded-bits.ll
[RISCV][ISel] Eliminate andi rd, rs1, -1 instructions (#89976)
2024-04-25 14:22:14 +08:00
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
…
rv64i-shift-sext.ll
…
rv64i-single-softfloat.ll
…
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
…
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
…
rv64xtheadba.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
rv64xtheadbb.ll
[RISCV] Simplify (srl (and X, Mask), Const) to TH_EXTU (#102802)
2024-08-16 14:23:00 +08:00
rv64xtheadbs.ll
…
rv64zba.ll
[RISCV] Expand mul X, C where C=2^N*(3,5,9)*(3,5,9) (#108100)
2024-09-11 07:33:06 -07:00
rv64zbb-intrinsic.ll
…
rv64zbb-zbkb.ll
…
rv64zbb.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
rv64zbc-intrinsic.ll
…
rv64zbc-zbkc-intrinsic.ll
…
rv64zbkb-intrinsic.ll
…
rv64zbkb.ll
[RISCV] Support zext.h mnemonic with Zbkb. (#96821)
2024-06-27 09:31:26 -07:00
rv64zbkx-intrinsic.ll
…
rv64zbs.ll
…
rv64zfh-half-convert-strict.ll
…
rv64zfh-half-convert.ll
[RISCV] Don't combine (sext_inreg (fmv_x_anyexth X), i16) with Zhinx.
2024-08-14 15:18:10 -07:00
rv64zfh-half-intrinsics.ll
…
rv64zfhmin-half-convert-strict.ll
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
2024-09-03 13:33:14 -07:00
rv64zfhmin-half-convert.ll
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
2024-09-03 13:33:14 -07:00
rv64zfhmin-half-intrinsics.ll
…
rv64zimop-intrinsic.ll
[RISCV] Zimop/Zcmop are ratified
2024-04-08 16:40:02 +08:00
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic-autoupgrade.ll
…
rv64zknh-intrinsic.ll
…
rv64zksed-intrinsic-autoupgrade2.ll
…
rv64zksed-intrinsic-autoupgrade.ll
…
rv64zksed-intrinsic.ll
…
rv64zksh-intrinsic-autoupgrade.ll
…
rv64zksh-intrinsic.ll
…
rvv-cfi-info.ll
[RISCV][CFI] Emit cfi_offset for every callee-saved vector registers (#100455)
2024-07-29 11:03:07 +08:00
sadd_sat_plus.ll
[RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
2024-02-04 23:15:58 -08:00
sadd_sat.ll
[RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
2024-02-04 23:15:58 -08:00
saverestore-scs.ll
…
saverestore.ll
…
scmp.ll
[SelectionDAG] Expand [US]CMP using arithmetic on boolean values instead of selects (#98774)
2024-07-16 20:56:18 +01:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
sdata-sections.ll
[RISCV] Let -data-sections also work on sbss/sdata sections (#87040)
2024-08-23 14:06:12 +01:00
sdiv-pow2-cmov.ll
…
select-and.ll
…
select-bare.ll
…
select-binop-identity.ll
[RISCV] Graduate Zicond to non-experimental (#79811)
2024-01-29 15:58:54 +00:00
select-cc.ll
…
select-const.ll
…
select-constant-xor.ll
…
select-optimize-multiple.ll
…
select-optimize-multiple.mir
[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)
2024-06-04 09:23:52 +08:00
select-or.ll
…
select-to-and-zext.ll
…
select.ll
[RISCV] Add coverage for select C, C1, C2 where (C1-C2)*[0,1] is cheap
2024-09-16 12:46:43 -07:00
selectcc-to-shiftand.ll
[RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. (#102034)
2024-08-06 20:27:14 -07:00
setcc-logic.ll
…
sext-zext-trunc.ll
[DAGCombiner][RISCV] CSE zext nneg and sext. (#82597)
2024-02-22 09:06:49 -08:00
sextw-removal-debug.mir
…
sextw-removal.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
shadowcallstack.ll
[RISCV] Add Zicfiss support to the shadow call stack implementation. (#68075)
2024-02-10 22:18:46 +08:00
shift-amount-mod.ll
…
shift-and.ll
…
shift-masked-shamt.ll
…
shifts.ll
…
shl-cttz.ll
[RISCV] Remove riscv-experimental-rv64-legal-i32. (#102509)
2024-08-09 11:48:48 -07:00
shl-demanded.ll
…
shlimm-addimm.ll
…
short-forward-branch-opt.ll
[RISCV] Enable PostRAScheduler for SiFive7 (#83166)
2024-02-29 09:57:15 -05:00
shrinkwrap-jump-table.ll
…
shrinkwrap.ll
…
sifive7-enable-intervals.mir
…
signbit-test.ll
[RISCV] Enable the TypePromotion pass from AArch64/ARM.
2024-02-13 09:57:48 -08:00
signed-truncation-check.ll
[RISCV] Select (and (sra x, c2), c1) as (srli (srai x, c2-c3), c3). (#101868)
2024-08-04 22:35:38 -07:00
sink-and-fold-crash.mir
[MachineSink][RISCV] Only call isConstantPhysReg or isIgnorableUse for uses. (#99363)
2024-07-17 13:06:58 -07:00
sink-icmp.ll
…
spill-fill-fold.ll
[RISCV] Use BuildPairF64 and SplitF64 for bitcast i64<->f64 on rv32 regardless of Zfa. (#85982)
2024-03-21 08:52:51 -07:00
spill-fpr-scalar.ll
[RISCV] Rewrite spill-fpr-scalar.ll test to not use vsetvli. NFC (#91428)
2024-05-08 11:33:05 +08:00
spir-kernel-cc.ll
…
split-offsets.ll
[RISCV] Enable -riscv-enable-sink-fold by default. (#82026)
2024-02-22 09:07:21 -08:00
split-sp-adjust.ll
…
split-store.ll
…
split-udiv-by-constant.ll
…
split-urem-by-constant.ll
…
srem-lkk.ll
…
srem-seteq-illegal-types.ll
[LegalizeTypes][RISCV] Use SPLAT_VECTOR_PARTS to legalize splat BUILD_VECTOR (#107290)
2024-09-04 19:14:18 -07:00
srem-vector-lkk.ll
[RISCV] Enable -riscv-enable-sink-fold by default. (#82026)
2024-02-22 09:07:21 -08:00
srodata.ll
[RISCV] Place mergeable small read only data into srodata section (#82214)
2024-03-11 13:57:06 +08:00
ssub_sat_plus.ll
[RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
2024-02-04 23:15:58 -08:00
ssub_sat.ll
[RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
2024-02-04 23:15:58 -08:00
stack-folding.ll
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stack-inst-compress.mir
[MachineFrameInfo] Refactoring around computeMaxcallFrameSize() (NFC) (#78001)
2024-03-18 10:37:59 -04:00
stack-offset.ll
[RISCV] Exploit sh3add/sh2add for stack offsets by shifted 12-bit constants (#87950)
2024-04-08 14:53:21 -07:00
stack-protector-target.ll
[RISCV] Use the thread local stack protector for Android targets (#87672)
2024-05-13 08:52:59 -07:00
stack-realignment-with-variable-sized-objects.ll
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stack-realignment.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
stack-slot-coloring.mir
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stack-slot-size.ll
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stack-store-check.ll
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subtarget-features-std-ext.ll
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switch-width.ll
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tagged-globals.ll
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tail-calls.ll
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
target-abi-invalid.ll
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target-abi-valid.ll
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thread-pointer.ll
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tls-models.ll
[RISCV] Support TLSDESC in the RISC-V backend (#66915)
2024-01-23 16:16:07 -08:00
tlsdesc-symbol.ll
[llvm][lld] Pre-commit tests for RISCV TLSDESC symbols
2024-03-20 13:39:39 -07:00
trunc-free.ll
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typepromotion-overflow.ll
Recommit "[TypePromotion] Support positive addition amounts in isSafeWrap. (#81690)"
2024-03-11 12:39:38 -07:00
uadd_sat_plus.ll
[LegalizeTypes][RISCV] Use signed promotion for UADDSAT if that's what the target prefers. (#102842)
2024-08-12 09:34:51 -07:00
uadd_sat.ll
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ucmp.ll
[LegalizeTypes][RISCV][LoongArch] Optimize promotion of ucmp. (#101366)
2024-07-31 17:18:27 -07:00
umulo-128-legalisation-lowering.ll
[MachineCombiner] Don't ignore PHI depths (#82025)
2024-03-14 11:47:29 -04:00
unaligned-load-store.ll
[RISCV] Improve constant materialisation for stores of i8 negative constants (#92131)
2024-05-14 19:08:04 +01:00
unfold-masked-merge-scalar-variablemask.ll
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unroll-loop-cse.ll
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
urem-lkk.ll
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urem-seteq-illegal-types.ll
[RISCV] Consider truncate semantics in performBUILD_VECTORCombine (#81168)
2024-02-08 11:28:06 -08:00
urem-vector-lkk.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
usub_sat_plus.ll
[LegalizeTypes][RISCV] Use SExtOrZExtPromotedOperands to promote operands for USUBSAT. (#102781)
2024-08-11 10:22:31 -07:00
usub_sat.ll
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vararg-ilp32e.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
vararg.ll
[RISCV] Lower the TransientStackAlignment to the ABI alignment for rv32e/rv64e.
2024-02-09 21:48:11 -08:00
vector-abi.ll
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verify-instr.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
vlenb.ll
[MachineLICM] Hoist copies of constant physical register (#93285)
2024-05-29 14:10:01 +08:00
vscale-demanded-bits.ll
Move stepvector intrinsic out of experimental namespace (#98043)
2024-08-28 12:48:20 +01:00
wide-mem.ll
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wide-scalar-shift-by-byte-multiple-legalization.ll
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wide-scalar-shift-legalization.ll
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xaluo.ll
[RISCV] Use SHL_ADD in remaining strength reduce cases for MUL (#89789)
2024-04-23 12:40:55 -07:00
xcvalu.ll
[RISCV] Rename XCValu cv.slet(u) to cv.sle(u). (#108481)
2024-09-12 21:39:01 -07:00
xcvbi.ll
[RISCV] Codegen support for XCVbi extension (#89719)
2024-05-08 11:22:16 +08:00
xcvbitmanip.ll
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xcvmac.ll
[RISCV] Implement Intrinsics for XCVmac Extension in CV32E40P (#83112)
2024-07-15 10:25:25 +10:00
xcvmem.ll
[RISCV] Codegen support for XCVmem extension (#76916)
2024-06-07 21:45:49 +08:00
xtheadfmemidx.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
xtheadmac.ll
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xtheadmemidx.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
xtheadmempair.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
zbb-cmp-combine.ll
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zcb-regalloc-hints.ll
[RISCV] Add regalloc hints for Zcb instructions. (#78949)
2024-01-23 09:33:06 -08:00
zcmp-additional-stack.ll
[RISCV] Align stack size down to a multiple of 16 before using cm.push/pop. (#86073)
2024-03-26 21:37:19 -07:00
zcmp-cm-popretz.mir
[RISCV] Add correct Uses, Defs, isReturn to Zcmp (#81039)
2024-02-07 14:30:45 -08:00
zcmp-cm-push-pop.mir
[RISCV] Add correct Uses, Defs, isReturn to Zcmp (#81039)
2024-02-07 14:30:45 -08:00
zcmp-prolog-epilog-crash.mir
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zcmp-with-float.ll
[RISCV] Remove stale comment from test. NFC (#81098)
2024-02-12 09:19:28 -08:00
zdinx-asm-constraint.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
zdinx-boundary-check.ll
[RISCV] Fix another RV32 Zdinx load/store addressing corner case.
2024-09-04 23:26:40 -07:00
zdinx-large-spill.mir
[RISCV] Preserve MMO when expanding PseudoRV32ZdinxSD/PseudoRV32ZdinxLD. (#85877)
2024-03-26 20:42:14 -07:00
zext-with-load-is-free.ll
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zfh-half-intrinsics-strict.ll
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zfh-half-intrinsics.ll
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zfhmin-half-intrinsics-strict.ll
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zfhmin-half-intrinsics.ll
[RISCV] Add test for llvm.round.i32.f16 RV64+Zfhmin/Zhinxmin. NFC
2024-09-01 12:15:00 -07:00
zfhmin-imm.ll
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zicfilp-indirect-branch.ll
[RISCV] Avoid using x7/t2 for indirect branches which need landing pad. (#68292)
2024-05-02 10:32:40 +08:00
zmmul.ll
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