307d1249ea
ucmp can be promoted with either sext or zext. RISC-V and LoongArch prefer sext for promoting i32 to i64 unless the inputs are known to be zero extended already. This patch uses the existing SExtOrZExtPromotedOperands function that is used by SETCC promotion to intelligently handle this.
261 lines
6.9 KiB
LLVM
261 lines
6.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefix=RV32I
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; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefix=RV64I
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define i8 @ucmp.8.8(i8 zeroext %x, i8 zeroext %y) nounwind {
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; RV32I-LABEL: ucmp.8.8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a2, a0, a1
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; RV32I-NEXT: sltu a0, a1, a0
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; RV32I-NEXT: sub a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.8.8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a0, a1
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; RV64I-NEXT: sltu a0, a1, a0
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; RV64I-NEXT: sub a0, a0, a2
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.16(i16 zeroext %x, i16 zeroext %y) nounwind {
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; RV32I-LABEL: ucmp.8.16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a2, a0, a1
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; RV32I-NEXT: sltu a0, a1, a0
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; RV32I-NEXT: sub a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.8.16:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a0, a1
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; RV64I-NEXT: sltu a0, a1, a0
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; RV64I-NEXT: sub a0, a0, a2
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.32(i32 %x, i32 %y) nounwind {
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; RV32I-LABEL: ucmp.8.32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a2, a0, a1
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; RV32I-NEXT: sltu a0, a1, a0
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; RV32I-NEXT: sub a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.8.32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sext.w a1, a1
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: sltu a2, a0, a1
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; RV64I-NEXT: sltu a0, a1, a0
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; RV64I-NEXT: sub a0, a0, a2
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.64(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: ucmp.8.64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a1, a3, .LBB3_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sltu a4, a1, a3
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; RV32I-NEXT: sltu a0, a3, a1
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; RV32I-NEXT: sub a0, a0, a4
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB3_2:
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; RV32I-NEXT: sltu a4, a0, a2
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; RV32I-NEXT: sltu a0, a2, a0
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; RV32I-NEXT: sub a0, a0, a4
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.8.64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a0, a1
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; RV64I-NEXT: sltu a0, a1, a0
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; RV64I-NEXT: sub a0, a0, a2
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
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ret i8 %1
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}
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define i8 @ucmp.8.128(i128 %x, i128 %y) nounwind {
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; RV32I-LABEL: ucmp.8.128:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lw a2, 4(a1)
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; RV32I-NEXT: lw a3, 4(a0)
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; RV32I-NEXT: lw a4, 8(a1)
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; RV32I-NEXT: lw a5, 12(a1)
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; RV32I-NEXT: lw a6, 12(a0)
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; RV32I-NEXT: lw a7, 8(a0)
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; RV32I-NEXT: beq a6, a5, .LBB4_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sltu t2, a6, a5
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; RV32I-NEXT: j .LBB4_3
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; RV32I-NEXT: .LBB4_2:
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; RV32I-NEXT: sltu t2, a7, a4
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; RV32I-NEXT: .LBB4_3:
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; RV32I-NEXT: lw a1, 0(a1)
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; RV32I-NEXT: lw t0, 0(a0)
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; RV32I-NEXT: beq a3, a2, .LBB4_5
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; RV32I-NEXT: # %bb.4:
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; RV32I-NEXT: sltu a0, a3, a2
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; RV32I-NEXT: j .LBB4_6
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; RV32I-NEXT: .LBB4_5:
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; RV32I-NEXT: sltu a0, t0, a1
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; RV32I-NEXT: .LBB4_6:
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; RV32I-NEXT: xor t1, a6, a5
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; RV32I-NEXT: xor t3, a7, a4
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; RV32I-NEXT: or t1, t3, t1
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; RV32I-NEXT: beqz t1, .LBB4_8
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; RV32I-NEXT: # %bb.7:
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; RV32I-NEXT: mv a0, t2
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; RV32I-NEXT: .LBB4_8:
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; RV32I-NEXT: beq a6, a5, .LBB4_11
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; RV32I-NEXT: # %bb.9:
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; RV32I-NEXT: sltu a4, a5, a6
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; RV32I-NEXT: bne a3, a2, .LBB4_12
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; RV32I-NEXT: .LBB4_10:
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; RV32I-NEXT: sltu a1, a1, t0
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; RV32I-NEXT: bnez t1, .LBB4_13
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; RV32I-NEXT: j .LBB4_14
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; RV32I-NEXT: .LBB4_11:
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; RV32I-NEXT: sltu a4, a4, a7
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; RV32I-NEXT: beq a3, a2, .LBB4_10
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; RV32I-NEXT: .LBB4_12:
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; RV32I-NEXT: sltu a1, a2, a3
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; RV32I-NEXT: beqz t1, .LBB4_14
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; RV32I-NEXT: .LBB4_13:
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; RV32I-NEXT: mv a1, a4
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; RV32I-NEXT: .LBB4_14:
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; RV32I-NEXT: sub a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.8.128:
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; RV64I: # %bb.0:
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; RV64I-NEXT: beq a1, a3, .LBB4_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: sltu a4, a1, a3
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; RV64I-NEXT: sltu a0, a3, a1
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; RV64I-NEXT: sub a0, a0, a4
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; RV64I-NEXT: ret
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; RV64I-NEXT: .LBB4_2:
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; RV64I-NEXT: sltu a4, a0, a2
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; RV64I-NEXT: sltu a0, a2, a0
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; RV64I-NEXT: sub a0, a0, a4
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.ucmp(i128 %x, i128 %y)
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ret i8 %1
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}
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define i32 @ucmp.32.32(i32 %x, i32 %y) nounwind {
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; RV32I-LABEL: ucmp.32.32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a2, a0, a1
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; RV32I-NEXT: sltu a0, a1, a0
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; RV32I-NEXT: sub a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.32.32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sext.w a1, a1
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: sltu a2, a0, a1
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; RV64I-NEXT: sltu a0, a1, a0
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; RV64I-NEXT: sub a0, a0, a2
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; RV64I-NEXT: ret
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%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @ucmp.32.32_sext(i32 signext %x, i32 signext %y) nounwind {
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; RV32I-LABEL: ucmp.32.32_sext:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a2, a0, a1
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; RV32I-NEXT: sltu a0, a1, a0
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; RV32I-NEXT: sub a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.32.32_sext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a0, a1
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; RV64I-NEXT: sltu a0, a1, a0
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; RV64I-NEXT: sub a0, a0, a2
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; RV64I-NEXT: ret
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%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @ucmp.32.32_zext(i32 zeroext %x, i32 zeroext %y) nounwind {
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; RV32I-LABEL: ucmp.32.32_zext:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a2, a0, a1
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; RV32I-NEXT: sltu a0, a1, a0
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; RV32I-NEXT: sub a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.32.32_zext:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a0, a1
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; RV64I-NEXT: sltu a0, a1, a0
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; RV64I-NEXT: sub a0, a0, a2
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; RV64I-NEXT: ret
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%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @ucmp.32.64(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: ucmp.32.64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a1, a3, .LBB8_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sltu a4, a1, a3
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; RV32I-NEXT: sltu a0, a3, a1
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; RV32I-NEXT: sub a0, a0, a4
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB8_2:
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; RV32I-NEXT: sltu a4, a0, a2
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; RV32I-NEXT: sltu a0, a2, a0
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; RV32I-NEXT: sub a0, a0, a4
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.32.64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a0, a1
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; RV64I-NEXT: sltu a0, a1, a0
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; RV64I-NEXT: sub a0, a0, a2
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; RV64I-NEXT: ret
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%1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
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ret i32 %1
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}
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define i64 @ucmp.64.64(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: ucmp.64.64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a1, a3, .LBB9_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sltu a4, a1, a3
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; RV32I-NEXT: sltu a0, a3, a1
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; RV32I-NEXT: j .LBB9_3
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; RV32I-NEXT: .LBB9_2:
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; RV32I-NEXT: sltu a4, a0, a2
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; RV32I-NEXT: sltu a0, a2, a0
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; RV32I-NEXT: .LBB9_3:
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; RV32I-NEXT: sub a0, a0, a4
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; RV32I-NEXT: srai a1, a0, 31
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ucmp.64.64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a2, a0, a1
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; RV64I-NEXT: sltu a0, a1, a0
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; RV64I-NEXT: sub a0, a0, a2
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; RV64I-NEXT: ret
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%1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
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ret i64 %1
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}
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