Kazushi (Jam) Marukawa 95ea50e4ad [VE] Correct LVLGen (LVL instruction insert pass) ...

SX Aurora VE uses an intermediate representation similar to VP as its MIR.
VE itself uses invidiual VL register as its own vector length register at
the hardware level.  So, LLVM needs to insert load VL (LVL) instruction just
before vector instructions if the value of VL is changed.  This LVLGen pass
generates LVL instructions for such purpose.  Previously, a bug is pointed
out in D91416.  This patch correct this bug and add a regression test.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D92716

2020-12-09 06:33:53 +09:00

4.6 KiB

Raw Blame History

View Raw