1e86abc914
The purpose of this code is to restrict overlap between source and destination registers. The tied input register is conceptually part of the destination. I can't see any reason why we need to prevent a partial undef tied source here, and skipping it reduces register pressure slightly. Differential Revision: https://reviews.llvm.org/D156709
277 lines
9.2 KiB
C++
277 lines
9.2 KiB
C++
//===- RISCVRVVInitUndef.cpp - Initialize undef vector value to pseudo ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a function pass that initializes undef vector value to
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// temporary pseudo instruction and remove it in expandpseudo pass to prevent
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// register allocation resulting in a constraint violated result for vector
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// instruction.
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//
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// RISC-V vector instruction has register overlapping constraint for certain
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// instructions, and will cause illegal instruction trap if violated, we use
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// early clobber to model this constraint, but it can't prevent register
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// allocator allocated same or overlapped if the input register is undef value,
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// so convert IMPLICIT_DEF to temporary pseudo instruction and remove it later
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// could prevent that happen, it's not best way to resolve this, and it might
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// change the order of program or increase the register pressure, so ideally we
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// should model the constraint right, but before we model the constraint right,
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// it's the only way to prevent that happen.
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//
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// When we enable the subregister liveness option, it will also trigger same
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// issue due to the partial of register is undef. If we pseudoinit the whole
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// register, then it will generate redundant COPY instruction. Currently, it
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// will generate INSERT_SUBREG to make sure the whole register is occupied
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// when program encounter operation that has early-clobber constraint.
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//
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//
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// See also: https://github.com/llvm/llvm-project/issues/50157
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/DetectDeadLanes.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-init-undef"
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#define RISCV_INIT_UNDEF_NAME "RISC-V init undef pass"
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namespace {
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class RISCVInitUndef : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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const RISCVSubtarget *ST;
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const TargetRegisterInfo *TRI;
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// Newly added vregs, assumed to be fully rewritten
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SmallSet<Register, 8> NewRegs;
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public:
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static char ID;
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RISCVInitUndef() : MachineFunctionPass(ID) {
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initializeRISCVInitUndefPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override { return RISCV_INIT_UNDEF_NAME; }
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private:
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bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
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const DeadLaneDetector &DLD);
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bool handleImplicitDef(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &Inst);
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bool isVectorRegClass(const Register R);
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const TargetRegisterClass *
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getVRLargestSuperClass(const TargetRegisterClass *RC) const;
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bool handleSubReg(MachineFunction &MF, MachineInstr &MI,
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const DeadLaneDetector &DLD);
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};
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} // end anonymous namespace
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char RISCVInitUndef::ID = 0;
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INITIALIZE_PASS(RISCVInitUndef, DEBUG_TYPE, RISCV_INIT_UNDEF_NAME, false, false)
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char &llvm::RISCVInitUndefID = RISCVInitUndef::ID;
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const TargetRegisterClass *
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RISCVInitUndef::getVRLargestSuperClass(const TargetRegisterClass *RC) const {
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if (RISCV::VRM8RegClass.hasSubClassEq(RC))
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return &RISCV::VRM8RegClass;
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if (RISCV::VRM4RegClass.hasSubClassEq(RC))
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return &RISCV::VRM4RegClass;
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if (RISCV::VRM2RegClass.hasSubClassEq(RC))
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return &RISCV::VRM2RegClass;
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if (RISCV::VRRegClass.hasSubClassEq(RC))
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return &RISCV::VRRegClass;
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return RC;
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}
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bool RISCVInitUndef::isVectorRegClass(const Register R) {
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const TargetRegisterClass *RC = MRI->getRegClass(R);
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return RISCV::VRRegClass.hasSubClassEq(RC) ||
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RISCV::VRM2RegClass.hasSubClassEq(RC) ||
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RISCV::VRM4RegClass.hasSubClassEq(RC) ||
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RISCV::VRM8RegClass.hasSubClassEq(RC);
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}
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static unsigned getUndefInitOpcode(unsigned RegClassID) {
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switch (RegClassID) {
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case RISCV::VRRegClassID:
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return RISCV::PseudoRVVInitUndefM1;
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case RISCV::VRM2RegClassID:
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return RISCV::PseudoRVVInitUndefM2;
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case RISCV::VRM4RegClassID:
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return RISCV::PseudoRVVInitUndefM4;
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case RISCV::VRM8RegClassID:
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return RISCV::PseudoRVVInitUndefM8;
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default:
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llvm_unreachable("Unexpected register class.");
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}
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}
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static bool isEarlyClobberMI(MachineInstr &MI) {
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return llvm::any_of(MI.defs(), [](const MachineOperand &DefMO) {
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return DefMO.isReg() && DefMO.isEarlyClobber();
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});
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}
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bool RISCVInitUndef::handleImplicitDef(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &Inst) {
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assert(Inst->getOpcode() == TargetOpcode::IMPLICIT_DEF);
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Register Reg = Inst->getOperand(0).getReg();
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if (!Reg.isVirtual())
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return false;
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bool HasOtherUse = false;
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SmallVector<MachineOperand *, 1> UseMOs;
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for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
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if (isEarlyClobberMI(*MO.getParent())) {
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if (MO.isUse() && !MO.isTied())
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UseMOs.push_back(&MO);
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else
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HasOtherUse = true;
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}
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}
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if (UseMOs.empty())
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return false;
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LLVM_DEBUG(
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dbgs() << "Emitting PseudoRVVInitUndef for implicit vector register "
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<< Reg << '\n');
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const TargetRegisterClass *TargetRegClass =
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getVRLargestSuperClass(MRI->getRegClass(Reg));
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unsigned Opcode = getUndefInitOpcode(TargetRegClass->getID());
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Register NewDest = Reg;
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if (HasOtherUse) {
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NewDest = MRI->createVirtualRegister(TargetRegClass);
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// We don't have a way to update dead lanes, so keep track of the
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// new register so that we avoid querying it later.
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NewRegs.insert(NewDest);
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}
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BuildMI(MBB, Inst, Inst->getDebugLoc(), TII->get(Opcode), NewDest);
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if (!HasOtherUse)
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Inst = MBB.erase(Inst);
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for (auto MO : UseMOs) {
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MO->setReg(NewDest);
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MO->setIsUndef(false);
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}
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return true;
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}
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bool RISCVInitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
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const DeadLaneDetector &DLD) {
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bool Changed = false;
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for (MachineOperand &UseMO : MI.uses()) {
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if (!UseMO.isReg())
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continue;
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if (!UseMO.getReg().isVirtual())
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continue;
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if (UseMO.isTied())
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continue;
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Register Reg = UseMO.getReg();
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if (NewRegs.count(Reg))
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continue;
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DeadLaneDetector::VRegInfo Info =
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DLD.getVRegInfo(Register::virtReg2Index(Reg));
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if (Info.UsedLanes == Info.DefinedLanes)
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continue;
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const TargetRegisterClass *TargetRegClass =
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getVRLargestSuperClass(MRI->getRegClass(Reg));
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LaneBitmask NeedDef = Info.UsedLanes & ~Info.DefinedLanes;
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LLVM_DEBUG({
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dbgs() << "Instruction has undef subregister.\n";
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dbgs() << printReg(Reg, nullptr)
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<< " Used: " << PrintLaneMask(Info.UsedLanes)
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<< " Def: " << PrintLaneMask(Info.DefinedLanes)
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<< " Need Def: " << PrintLaneMask(NeedDef) << "\n";
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});
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SmallVector<unsigned> SubRegIndexNeedInsert;
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TRI->getCoveringSubRegIndexes(*MRI, TargetRegClass, NeedDef,
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SubRegIndexNeedInsert);
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Register LatestReg = Reg;
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for (auto ind : SubRegIndexNeedInsert) {
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Changed = true;
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const TargetRegisterClass *SubRegClass =
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getVRLargestSuperClass(TRI->getSubRegisterClass(TargetRegClass, ind));
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Register TmpInitSubReg = MRI->createVirtualRegister(SubRegClass);
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BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
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TII->get(getUndefInitOpcode(SubRegClass->getID())),
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TmpInitSubReg);
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Register NewReg = MRI->createVirtualRegister(TargetRegClass);
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BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
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TII->get(TargetOpcode::INSERT_SUBREG), NewReg)
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.addReg(LatestReg)
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.addReg(TmpInitSubReg)
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.addImm(ind);
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LatestReg = NewReg;
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}
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UseMO.setReg(LatestReg);
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}
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return Changed;
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}
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bool RISCVInitUndef::processBasicBlock(MachineFunction &MF,
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MachineBasicBlock &MBB,
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const DeadLaneDetector &DLD) {
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bool Changed = false;
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
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MachineInstr &MI = *I;
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if (ST->enableSubRegLiveness() && isEarlyClobberMI(MI))
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Changed |= handleSubReg(MF, MI, DLD);
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if (MI.isImplicitDef()) {
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auto DstReg = MI.getOperand(0).getReg();
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if (isVectorRegClass(DstReg))
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Changed |= handleImplicitDef(MBB, I);
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}
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}
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return Changed;
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}
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bool RISCVInitUndef::runOnMachineFunction(MachineFunction &MF) {
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ST = &MF.getSubtarget<RISCVSubtarget>();
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if (!ST->hasVInstructions())
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return false;
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MRI = &MF.getRegInfo();
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TII = ST->getInstrInfo();
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TRI = MRI->getTargetRegisterInfo();
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bool Changed = false;
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DeadLaneDetector DLD(MRI, TRI);
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DLD.computeSubRegisterLaneBitInfo();
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for (MachineBasicBlock &BB : MF)
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Changed |= processBasicBlock(MF, BB, DLD);
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return Changed;
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}
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FunctionPass *llvm::createRISCVInitUndefPass() { return new RISCVInitUndef(); }
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