Oliver Stannard 9f02950a15 [ARM] Allow spilling FPSCR for MVE adc/sbc intrinsics (#115174) ...

The MVE VADC and VSBC instructions read and write a carry bit in FPSCR,
which is exposed through the intrinsics. This makes it possible to write
code which has the FPSCR live across a function call, or which uses the
same value twice, so it needs to be possible to spill and reload it.

There is a missed optimisation in one of the test cases, where we reload
the FPSCR from the stack despite it still being live, I've not found a
simple way to prevent the register allocator from doing this.

2024-11-07 11:23:49 +00:00

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