83d9ed29c1
`LowerDYNAMIC_STACKALLOC()` emits the `dynamic_stackalloc` chain operand instead of the chain produced by the `NVPTXISD::DYNAMIC_STACKALLOC`. Fix this behavior and don't produce an unnecessary `ISD::MERGE_VALUES`.
30 lines
1.0 KiB
LLVM
30 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -march=nvptx64 -mattr=+ptx73 -mcpu=sm_52 | FileCheck %s
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target triple = "nvptx64-nvidia-cuda"
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define void @foo(i64 %a, ptr %p0, ptr %p1) {
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; CHECK-LABEL: foo(
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; CHECK: {
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; CHECK-NEXT: .reg .b64 %rd<8>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.u64 %rd1, [foo_param_0];
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; CHECK-NEXT: add.s64 %rd2, %rd1, 7;
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; CHECK-NEXT: and.b64 %rd3, %rd2, -8;
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; CHECK-NEXT: alloca.u64 %rd4, %rd3, 16;
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; CHECK-NEXT: cvta.local.u64 %rd4, %rd4;
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; CHECK-NEXT: ld.param.u64 %rd5, [foo_param_1];
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; CHECK-NEXT: alloca.u64 %rd6, %rd3, 16;
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; CHECK-NEXT: cvta.local.u64 %rd6, %rd6;
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; CHECK-NEXT: ld.param.u64 %rd7, [foo_param_2];
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; CHECK-NEXT: st.u64 [%rd5], %rd4;
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; CHECK-NEXT: st.u64 [%rd7], %rd6;
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; CHECK-NEXT: ret;
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%b = alloca i8, i64 %a, align 16
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%c = alloca i8, i64 %a, align 16
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store ptr %b, ptr %p0, align 8
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store ptr %c, ptr %p1, align 8
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ret void
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}
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